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US 6,584,576 B1Granted
Memory system using complementary delay elements to reduce rambus module timing skew
AssigneeKingston Technology Corporation
InventorRamon S. Co
Life of this patent
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AssigneeKingston Technology Corporation
InventorRamon S. Co
Estimating the term…
An improvement in a Rambus memory system of the type used in personal computers. On a module level, each RIMM (Rambus Interface Memory Module) includes a positive and a negative module time delay element on the CTM (clock to master) clock line. On a system level, where a motherboard has a plurality of RIMMs coupled to a chipset (i.e. memory controller), a positive or negative system time delay element is placed on the CFM (clock from master line). By virtue of the module and system time delay elements, the clock timing can be adjusted from the data timing, whereby the overall TQ (timing skew between clock and data) can be advantageously reduced to allow more RIMMs to be placed on the same motherboard. What is more, the module and system delays also improve timing margins on the standard Rambus channel so as to increase the robustness of a conventional Rambus system.
For a RIMM (Rambus Interface Memory Module) having a plurality of synchronously controlled RDRAM memory elements, each of said plurality of RDRAM memory elements coupled to each of an address line to be connected to a memory controller, a data bus line to be connected to the memory controller, and a clock signal path to be connected to the memory controller whereby clock control signals are transmitted between said plurality of RDRAM memory elements and the memory controller, and each of said address line, said data bus line, and said clock signal path are to be respectively connected to the memory controller in electrical series with said RIMM, the improvement comprising time delay means located within said clock signal path so that the timing of said clock control signals transmitted over said clock signal path are adjusted relative to the timing of data signals transmitted over said data bus line so that any error between the timing of said clock control signals and said data signals can be reduced.
A synchronously controlled memory system having a plurality of RIMMs (Rambus Interface Memory Modules) interconnected to one another and coupled to each of an address line connected to a memory controller, a data bus line connected to the memory controller, and a clock signal path connected to the memory controller whereby clock control signals are transmitted between said plurality of RIMMs and the memory controller, each of said address line, said data bus line and said clock signal path being respectively connected in electrical series with each of said plurality of RIMMs, and a time delay located between said clock signal path and the memory controller so that the timing of said clock control signals transmitted over said clock signal path are adjusted independently of the timing of data signals transmitted over said data bus line so that any error between the timing of said clock signals and said data signals can be reduced.
Dependencies are inferred from the claim text.