Flexible phase-locked loop system to indicate synchronization using difference between internal and external clock signals

A method for synchronizing one of a plurality of external clock signals to a timing signal, comprising:

• (a) selecting to receive one of a plurality of external clock signals;
• (b) detecting a difference between an internal clock signal and the selected one of a plurality of external clock signal and generating a first control signal representing the difference;
• (c) generating a first timing signal based on said first control signal;
• (d) dividing said first timing signal by a first predetermined number to provide an output signal;
• (e) detecting a difference between the first timing signal and a second timing signal and generating a second control signal representing the difference;
• (f) generating a third timing signal based on said second control signal;
• (g) dividing said third timing signal by a second predetermined number to provide the second timing signal;
• (h) dividing the third timing signal by a third predetermined number to provide said internal clock signal.

A system for synchronizing signals in a processor-based system, comprising:

• a memory for storing instruction sequences by which the processor-based system is processed,
• a processor coupled to the memory for processing the instruction sequences, wherein the instruction sequences cause the processor to (a) select to receive one of a plurality of external clock signals;
• (b) detect a difference between an internal clock signal and the selected one of a plurality of external clock signal and generating a first control signal representing the difference;
• (c) determine if the first control signal has a first value that is within a predetermined range;
• (d) if so, calculating a second value representing an absolute value of a difference between a current value of the first control signal and a previous value of the first control signal, otherwise repeating (c);
• (e) determining if the second value is less than a third value;
• (f) if so, resetting the output signal upon receipt of an edge of said selected one of the plurality of external clock signals, otherwise repeating (c);
• (g) determining if a timing difference between the output signal and the selected one of the plurality of external clock signals is substantially zero;
• (h) if so, issuing a signal indicative of synchronization, otherwise repeating (c).

A computer program product, comprising:

• a computer usable medium having computer program code embodied therein for accessing at least one readable storage in a processor-based system, the computer program product having:
• (a) computer readable program code for (a) selecting to receive one of a plurality of external clock signals;
• (b) computer readable program code for detecting a difference between an internal clock signal and the selected one of a plurality of external clock signal and generating a first control signal representing the difference;
• (c) computer readable program code for (c.1) determining if the first control signal has a first value that is within a predetermined range, (c.2) if so, calculating a second value representing an absolute value of a difference between a current value of the first control signal and a previous value of the first control signal, otherwise repeating (c.1);
• (d) computer readable program code for (d.1) determining if the value is less than a third value;
• (d.2) if so, resetting the output signal upon receipt of an edge of said selected one of the plurality of external clock signals, otherwise repeating (c.1);
• (e) computer readable program code for (e.1) determining if a timing difference between the output signal and the selected one of the plurality of external clock signals is substantially zero, (e.2) if so, issuing a signal indicative of synchronization, otherwise repeating (c.1).