Placing a computer system into a sleeping state
AssigneeIntel Corporation
InventorsRuss Wunderlich, Yan Li, Mani Ayyar, Gary N. Hammond
Life of this patent
Estimating the term…
Abstract
A computer system enters or exits a sleeping state, such as the ACPI “S1” state, in response to a sleep or wake event. Upon detecting the sleep or wake event, a system component generates a sleep or wake signal that instructs the computer to enter or exit the sleeping state. This sleep or wake signal is of a type to which the computer's processor does not respond. Therefore, a PMI signal is asserted in response to the sleep or wake signal. The PMI signal, when asserted, causes the processor to halt program execution.
Claims20
A computer system comprising:
- a sleep management component that generates a sleep signal instructing the computer to enter a sleeping state in which program execution ceases;
- a central processor of the computer that is not configured to respond to the sleep signal;
- and
- a system management component, including the computer's basic input/output system (BIOS), that is configured, in response to the sleep signal, to place the processor in a halt state in which program execution ceases.
A computer system comprising:
- a processor having no STPCLK pin;
- a peripheral bus connected to a peripheral device that is operable to generate sleep and wake events;
- an I/O firmware bridge that is coupled to the peripheral bus to receive the sleep and wake events generated by the peripheral device and that is configured to assert or deassert a STPCLK signal and assert a system management interrupt (SMI) signal upon receiving one of the sleep or wake events;
- an edge detection circuit connected to receive the STPCLK signal and configured to:
- assert a general purpose input/output (GPIO) signal upon detecting a rising or falling edge of the STPCLK signal;
- and
- deliver the GPIO signal to the I/O firmware bridge to trigger assertion of the SMI signal;
- and
- a basic input/output system (BIOS) that is configured to place the processor in or remove the processor from a HALT state in response to the SMI signal.
A computer system comprising:
- a sleep management component that generates a wake signal instructing the computer to exit a sleeping state in which program execution ceases;
- a central processor of the computer that is configured to enter a halt state while the computer is in the sleeping state and that is not configured to respond to the wake signal;
- and
- a system management component, including the computer's basic input/output system (BIOS), that is configured, in response to the wake signal, to remove the processor from the halt state.
A method for use in placing a computer system in a low power state comprising:
- detecting a sleep event indicating that the computer system should enter the low power state;
- asserting a STPCLK signal in response to the sleep event;
- asserting a platform management interrupt (PMI) signal in response to the STPCLK signal;
- and
- halting program execution in response to the PMI signal.
Dependencies are inferred from the claim text.