US 6,584,553 B2 · Method and system for sequentially programming memory-containing integrated circuits

Abstract

Data to be programmed into memory-containing ICs is divided into a number (X) of blocks preferably equal to the number of sockets on a common programmer unit. A pick-up head inserts an unprogrammed IC into the first socket and the IC is programmed with a first data block A. While programming is occurring the pick-up head fetches an unprogrammed IC and inserts it into a second socket, whereupon both ICs are simultaneously programmed with the second data block B. During this time an unprogrammed IC is fetched and inserted into a third socket, whereupon all socketed ICs are simultaneously programmed with a third data block C. Eventually the first IC is fully programmed and is replaced with an unprogrammed IC and the cycle continues until all ICs to be programmed have been programmed. Multiple pick-up heads and/or multi-socketed programming units can be used.

Claims21

Dependent claims

A method of sequentially programming memory-containing integrated circuits (ICs) with data, comprising the following steps:

(a) providing a number of programming sites equal to X;
(b) dividing said data into X memory blocks;
(c) coupling a first IC to a first of said sites and programming memory in said IC with a first of said memory blocks;
and
(d) coupling a second IC to a second of said sites and simultaneously programming memory in said first IC and said second IC with a second of said memory blocks.

2 more elements

A system to sequentially program memory-containing integrated circuits (ICs) with data of size Q bytes, the system comprising:

a first programmer unit having X program sites connected thereto;
a first movable pick-up head disposed to fetch unprogrammed said ICs and to coupled them one at a time to a chosen one of said X program sites;
a controller unit;
said head, coupled to said controlled unit, and disposed to couple a first of the unprogrammed said ICs to a first of said program sites;
means for programming, coupled to said controller, to program a first block of data of size Q/X into the first IC;
said head further disposed to couple a second of the unprogrammed said ICs to a second of said program sites;
said means for programming is further controlled to program simultaneously a second block of data of size Q/X into said first IC and into the second IC;
said head further disposed to couple a third of the unprogrammed said ICs to a third of said program sites;
said means for programming further controlled to program simultaneously a third block of data of size Q/X into said first IC, into said second IC, and into the third IC;
wherein if X=3, said first IC is fully programmed.

7 more elements

Dependencies are inferred from the claim text.

Method and system for sequentially programming memory-containing integrated circuits

Life of this patent

Method and system for sequentially programming memory-containing integrated circuits

Life of this patent

Abstract

Claims21