Shared cache structure for temporal and non-temporal instructions
AssigneeIntel Corporation
InventorsSalvador Palanca, Niranjan L. Cooray, Angad Narang, Vladimir Pentkovski, Steve Tsai
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Abstract
A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
Claims15
An apparatus for processing temporal and non-temporal data comprising:
- a memory means;
- a processor means coupled to the memory means, the processor means to execute instructions to process non-temporal data and
- temporal data;
- cache memory means coupled to the processor means, the cache memory means having at least two cache ways each comprising a plurality of sets, each of the plurality of sets having a first bit indicative of whether one of the at least two cache ways contains non-temporal data that can be replaced first and a second bit indicative of an order of data entry in a corresponding cache way;
- and
- wherein the processor means accesses data from the memory means or the cache memory means.
The apparatus of wherein
- the second bit is a least recently used bit.
Dependencies are inferred from the claim text.