Highly efficient design of storage array for use in first and second cache spaces and memory subsystems

A processing system comprising:

• a system memory;
• a cache memory comprising first and second peer cache memory spaces;
• a first table for storing tags associated with data stored in the first cache memory space;
• a second table for storing tags associated with data stored in the second cache memory space;
• processing circuitry operable to:
• access a plurality of blocks of data from said system memory in response to a plurality of addresses;
• store said blocks of data accessed from said system memory within said first cache memory space, said blocks of data associated with a set of tags in said first table;
• store a selected block of said blocks of data accessed from said system memory within said second cache memory space, and said block associated with a tag in said second table;
• generate a read address including a tag field;
• compare said tag field of said read address with said tag in said second table associated with said selected block and access said selected block from said second cache memory space when said tag field and said tag in said second table match;
• and
• compare said tag field of said read address with said set of tags in said first table when said tag field and said tag in said second table do not match and access a corresponding block in said first cache memory space when said tag field and a tag in said first table match.