Microwave paging architecture
AssigneeNational Semiconductor Corporation
InventorDavid Weigand
Life of this patent
Estimating the term…
Abstract
A Time Division Multiple Access (TDMA) mobile station architecture consuming less power and random access memory (RAM) is presented herein. The mobile station includes a coprocessor which executes frame programs. The frame programs include instructions which address memory. The memory includes page addresses and byte addresses. The instructions of the frame program address the page addresses and byte addresses. A particular page address is reserved as a null page address, wherein any instruction addressing the null page address causes the memory locations of the most recently accessed memory page to be accessed.
Claims10
A method for controlling radio components, said method comprising:
- executing a first instruction, said first instruction comprising a first page address and a first byte address;
- fetching a second instruction, said second instruction comprising a second page address and a second byte address;
- and
- accessing a memory location associated with the first page address and the second byte address responsive to fetching the second instruction.
A system for controlling radio components, said system comprising:
- a microsequencer for executing a first instruction, said first instruction comprising a first page address and a first byte address in a radio frequency random access memory (RF RAM) and for fetching a second instruction, said second instruction comprising a second page address and a second byte address;
- and
- an execution engine for accessing a memory location in the RF RAM associated with the first page address and the second byte address, responsive to fetching the second instruction.
A method for controlling radio components, said method comprising:
- executing a first instruction, said first instruction comprising a first page address and a first byte address;
- fetching a second instruction, said second instruction comprising a second page address and a second byte address;
- accessing a first memory location associated with the first page address and the second byte address responsive to fetching the second instruction, wherein the second page address is a predetermined address;
- and
- accessing a second memory location associated with the second page address and the second byte address responsive to fetching the second instruction, wherein the second page address is not the predetermined address.
A system for executing instructions, said system comprising:
- a microcode random access memory (RAM) for storing a first instruction and a second instruction, wherein the first instruction comprises a first page address and a first byte address, and wherein the second instruction comprises a second page address and a second byte address;
- a fetch stage for fetching the second instruction from the microcode RAM;
- a decode stage for determining whether the second page address is a predetermined null address;
- and
- an execution engine for accessing a memory location in a radio frequency (RF) RAM associated with the first page address and the second byte address, responsive to the decode stage determining that the second page address is the predetermined null address and for accessing a memory location in the RF RAM associated with the second page address and the second byte address, responsive to the decode stage determining that the second page address is not the predetermined null address.
Dependencies are inferred from the claim text.