Bus transaction accelerator for multi-clock systems

A method of accelerating status register transactions in multi-clock systems, comprising the steps of:

• (a.) providing a first, a second, and a third electronic data storage devices, each having an input and an output;
• (b.) loading an external system interrupt request into the first data storage device;
• (c.) clocking the first data storage device by an external system clock, whereby the interrupt request is made available to the second data storage device;
• (d.) passing the interrupt request to the second data storage device;
• (e.) clocking the second data storage device by a host system clock, whereby the interrupt request is made available to the third data storage device;
• (f.) passing the interrupt request to the third data storage device;
• (g.) clocking the third data storage device by the host system clock, whereby the interrupt request is synchronized with the host system clock and made available to a host system;
• (h.) passing the output of the third data storage device to the host system;
• (i.) clearing the first and second data storage devices;
• and
• (j.) clearing the third data storage device after the host system has read the system interrupt request.

A method of accelerating bus transactions in multi-clock systems, comprising the steps of:

• providing first, and a second electronic data storage devices, each having a predetermined number of data inputs and data outputs;
• making a predetermined number of data bits available to the data inputs of the first data storage device;
• clocking the first data storage device by a host system clock, said predetermined number of data bits being available to the second storage device;
• loading the data bits into the data inputs of the second storage device;
• clocking the second data storage device by an external system clock, the data bits being available to an external system;
• and
• passing the data bits to the external system;
• providing an enabling circuit for the second data storage device;
• loading a host system write-enable signal into the enabling circuit;
• synchronizing the host system write-enable signal to the external system clock;
• and
• passing the synchronized write-enable signal from the enabling circuit to an enable input of the second data storage device.

A status register for a first system for communication with a second system operating at a different clock rate than said first system, said first system having a first clock operating at a first clock rate and comprising:

• first, second and third serially connected bistable devices, each of said bistable devices having a clock input terminal, an output terminal and a clear terminal;
• said clock input of said first bistable device being coupled to said first clock;
• said clock inputs of said second and third bistable devices coupled to a second clock from said second system operating at a clock rate different from said first clock rate;
• the output of said second and third bistable devices being coupled through an AND gate to the clear terminal of said first bistable device to reset the first bistable device upon receipt of an output from said second bistable device.

A status register for a first system for communication with a second system operating at a different clock rate than said first system, said first system having a first clock operating at a first clock rate and comprising:

• first, second and third serially connected bistable devices, each of said bistable devices having a clock input terminal, an output terminal and a clear terminal, said first and third bistable devices having an enable input and a second input and said second bistable device having a single input terminal;
• said clock input of said first bistable device being coupled to said first clock;
• said clock inputs of said second and third bistable devices coupled to a second clock from said second system operating at a clock rate different from said first clock rate;
• the output of said second and third bistable devices being coupled through an AND gate to the clear terminal of said first bistable device to reset the first bistable device upon receipt of an output from said third bistable device and said second bistable device.

A control register for a first system for communication with a second system operating at a different clock rate than said first system, said first system having a first clock operating at a first clock rate and comprising:

• first and second serially connected bistable devices, each having an output terminal, first and second input terminals, a clock terminal and a clear terminal, the output terminal of said first bistable device coupled to one of the input terminals of said second bistable device;
• third and fourth serially connected bistable devices, each having an output terminal, an input terminal, a clock terminal and a clear terminal;
• a first AND gate coupled to said first input terminal of said third bistable device;
• a second AND gate coupled to the clear terminal of said third bistable device;
• clear circuitry coupled to the clear terminals of said first, second and fourth bistable devices and to said second AND gate;
• circuitry coupling one of said input terminals of said first bistable device and the output terminal of said third bistable device to the input of said first AND gate;
• said clock terminals of said first and third bistable devices coupled to said first clock and said clock terminals of said second and fourth bistable devices coupled to said second clock
• the output terminal of said fourth bistable device coupled to the other input terminal of said second bistable device.

A control register for a first system for communication with a second system operating at a different clock rate than said first system, said first system having a first clock operating at a first clock rate and comprising:

• first and second serially connected bistable devices, each having an output terminal, first and second input terminals, a clock terminal and a clear terminal;
• third, fourth and fifth serially connected bistable devices, each having an output terminal, an input terminal, a clock terminal and a clear terminal, the output terminal of said first bistable device coupled to one of the input terminals of said second bistable device;
• a first AND gate coupled to said first input terminal of said third bistable device;
• a second AND gate coupled to the clear terminal of said third bistable device;
• clear circuitry coupled to the clear terminals of said first, second and fourth and fifth bistable devices and to said second AND gate;
• circuitry coupling one of said input terminals of said first bistable device and the output terminal of said third bistable device to the input of said first AND gate;
• said clock terminals of said first and third bistable devices coupled to said first clock and said clock terminals of said second and fourth and fifth bistable devices coupled to said second clock;
• the output terminal of said fourth bistable device also being coupled to said clear terminal of said third bistable device;
• and
• the output terminal of said fifth bistable device coupled to the other input terminal of said second bistable device.