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US 6,584,528 B1Granted
Microprocessor allocating no wait storage of variable capacity to plurality of resources, and memory device therefor
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTakashi Kurafuji, Akira Yamada
Life of this patent
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Abstract
A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the plurality of banks and the first and second buses, and a processor core connected to the first and second buses and the single port memory. The bus switch circuit may be controlled statically, independent of activities on the buses, or may be controlled dynamically according to the activities.
Claims7
A microprocessor, comprising:
- a first bus and a second bus capable of operating simultaneously;
- a memory divided into a plurality of banks;
- a bus switch circuit provided between said plurality of banks and said first and said second buses;
- and
- a processor core connected to said first bus, said second bus and said memory,
- wherein each of said plurality of buys switches is provided between corresponding one of said plurality of banks and said first and said second buses, and controlled by bus designating information given to said corresponding bank;
- and
- wherein each of said plurality of bus switches includes an exception signal generating portion for generating, when detecting occurrence of an access to a corresponding bank on a bus other than the bus coupled to the corresponding bank, an exception for application to said processor core.
5 more elements
A microprocessor, comprising:
- a first bus and a second bus capable of operating simultaneously;
- a memory divided into a plurality of banks;
- a bus switch circuit provided between said plurality of banks and said first and said second buses;
- and
- a processor core connected to said first bus, said second bus and said memory,
- wherein said bus switch circuit includes a plurality of bus switches each provided between corresponding one of said plurality of banks and said first and said second buses, and controlled by bus designating information given to said corresponding bank;
- and
- wherein each of said plurality of bus switches includes an access request detecting portion for detecting an access request on said first bus or on said second bus, and coupling the bus with the access request to the input/output path of the corresponding bank.
5 more elements
A microprocessor, comprising:
- a first bus and a second bus capable of operating simultaneously;
- a memory divided into a plurality of banks;
- a bus switch circuit provided between said plurality of banks and said first and said second buses;
- and
- a processor core connected to said first bus, said second bus and said memory,
- wherein said bus switch circuit includes a plurality of bus switches each provided between corresponding one of said plurality of banks and said first and said second buses, and controlled by bus designating information given to said corresponding bank;
- and
- wherein each of said plurality of bus switches includes a simultaneous access detecting portion for generating, when detecting occurrence of simultaneous access requests to a same bank on said first bus and said second bus, an exception for application to said processor core.
5 more elements
Dependencies are inferred from the claim text.