Inserting bus inversion scheme in bus path without increased access latency

A computer system, comprising:

• a bus;
• a processor and a bus device coupled to the bus;
• a first bus unit coupled between the bus device and the bus, the first bus unit including:
• a first conditional bus inverter to conditionally invert each of a plurality of bus signals from the bus device to the bus;
• first decision logic to make a determination whether to invert the plurality of bus signals with the first conditional bus inverter based on a condition;
• a second bus unit coupled between the bus device and the bus, the second bus unit including logic to perform a data-related function at the same time the first decision logic is determining whether to invert the plurality of bus signals;
• and
• a third bus unit coupled between the processor and the bus.

A method, comprising:

• requesting data from a first bus device;
• providing the data in the form of data signals from the first bus device to first and second bus units, wherein the first bus unit includes a conditional inverter to invert the data signals based on a condition;
• determining by the first bus unit if the condition is met;
• inverting the data signals if the condition is met and not inverting the data signals if the condition is not met;
• performing a function in the second bus unit at the same time as the determining and inverting, such that time required for determining and inverting does not contribute to bus latency cumulatively with time required for performing;
• and
• transmitting the data over a bus, whether or not the data signals are inverted.