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US 6,584,525 B1Granted
Adaptation of standard microprocessor architectures via an interface to a configurable subsystem
OwnerEdwin E. Klingmaninventor
Life of this patent
Estimating the term…
Abstract
A system for extending standard processors using either undefined op-codes or sparse address spaces to maintain the use of legacy processor tools and reduce the complexity of the design process. The disclosure describes a method and apparatus for adding circuitry to processing units that allows partitioning of the design into a fixed processing unit derivative and a configurable subsystem. The legacy processor unit language tools work with the fixed processing unit derivative while the logic design tools work well with the configurable subsystem. In one embodiment, the configurable subsystem is implemented with easily available programmable Logic Devices (PLD's and FPGA's).
Claims29
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- having at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus;
- and
- at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes the activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that references an unassigned location in the space to cause activation of the select signal;
- and
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
3 more elements
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus, wherein the control signals on the extended bus include a ready signal connected to the I/O port;
- and
- at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit, the processing unit receiving the ready signal from the I/O port, and an inactive state of the ready signal stalling the processing unit;
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
2 more elements
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus;
- and
- at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of an unassigned location in the space causes the activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions residing in the inexhaustively decoded space, the instruction processing unit executing an instruction at an unassigned location in the inexhaustively decoded space to cause activation of the select signal;
- and
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
3 more elements
A method of operating a processing system with an extended bus, the method comprising the steps of:
- forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;
- executing an instruction in a functional unit, connected to the central bus of the processing system, and having an inexhaustively decoded space, the instruction using an unassigned location in the inexhaustively decoded space to cause activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that makes a reference to an unassigned location of the space to cause activation of the select signal;
- and
- transferring data between the central bus and the extended bus in response to executing the instruction causing the activation of the select signal.
1 more element
A method of operating a processing system with an extended bus, the method comprising the steps of:
- forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;
- executing an instruction in a functional unit, connected to the central bus of the processing system, and having an inexhaustively decoded space, the instruction using an unassigned location in the inexhaustively decoded space to cause activation of the select signal on the extended bus, wherein the functional unit includes an instruction processing unit for executing instructions residing in the inexhaustively decoded space, the instruction processing unit executing an instruction at an unassigned location in the inexhaustively decoded space to cause activation of the select signal;
- and
- transferring data between the central bus and the extended bus in response to executing the instruction causing the activation of the select signal.
1 more element
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal, relating to the address and data signals on the extended bus;
- at least one functional unit connected to the central bus, the at least one functional unit having an inexhaustively decoded space, wherein use of unassigned location in the inexhaustively decoded space causes the activation of the select signal on the extended bus;
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus;
- and
- a configurable subsystem having an interface connected to the extended bus and activating the interface upon receiving an activated select signal, the configurable subsystem for implementing the functional extension.
3 more elements
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus;
- and
- at least one functional unit connected to the central bus, wherein the functional unit includes an instruction processing unit for executing instructions and a register set residing in an inexhaustively decoded space, the instruction processing unit configured to execute an instruction that references an unassigned location in said space to cause activation of the select signal;
- and
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
3 more elements
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus;
- and
- means for processing, connected to the central bus, and including means for executing instructions and means for storing data, said storing means residing in an inexhaustively decoded space, wherein the means for executing institutions is configured to execute an instruction that references an unassigned location in said space to cause activation of the select signal;
- and
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
3 more elements
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus;
- and
- at least one functional unit connected to the central bus, wherein the functional unit includes an instruction processing unit for executing instructions in an instruction space, the instruction processing unit configured to execute an instruction at an unassigned location in the instruction space to cause activation of the select signal;
- and
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
3 more elements
A processing system having an extended bus, the processing system comprising:
- a central bus for carrying address, data and control signals relating to the address and data on the central bus;
- at least one I/O port, connected to the central bus, the I/O port forming the extended bus having address and data signals and control signals, including a select signal relating to the address and data signals on the extended bus;
- and
- means for processing, connected to the central bus, and including means for executing instructions in an instruction space, wherein the means for executing instructions is configured to execute an instruction at an unassigned location in the instruction space to cause activation of the select signal;
- and
- wherein data is transferable between the central bus and the extended bus when the select signal is activated on the extended bus.
3 more elements
A method of operating a processing system with an extended bus, the method comprising the steps of:
- forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;
- executing an instruction in a functional unit connected to the central bus of the processing system to cause activation of the select signal, wherein the functional unit includes an instruction processing unit and a register set residing in the inexhaustively decoded space, the instruction processing unit executing an instruction that makes a reference to an unassigned location of the space to cause activation of the select signal;
- and
- transferring data between the central bus and the extended bus in response to executing the instruction causing activation of the select signal.
1 more element
A method of operating a processing system with an extended bus, the method comprising the steps of:
- forming the extended bus from an I/O port connected to a central bus of the processing system, wherein the extended bus includes address data and control signals, including a select signal relating to the address and data signals on the extended bus;
- executing an instruction in a functional unit connected to the central bus of the processing system to cause activation of the select signal, wherein the functional unit includes an instruction processing unit for executing instructions residing in an instruction space, the instruction processing unit executing an instruction at an unassigned location in the instruction space to cause activation of the select signal;
- and
- transferring data between the central bus and the extended bus in response to executing the instruction causing activation of the select signal.
1 more element
Dependencies are inferred from the claim text.