Communication DMA device for freeing the data bus from the CPU and outputting divided data
AssigneeSanyo Electric Co., Ltd.
InventorHideki Ishibashi
Life of this patent
Estimating the term…
Abstract
When the data bus is cut off from the CPU (1) and the transmission ready signal (TXRDY) is activated, the DMA control circuit (10) reads 32 bits of data at once according to the lead address of the destined area for storage in the DRAM (2) and the address width that are set by the CPU (1), and stores the data in the transmission buffer (16). The selector (17) selects 8 bits of data at a time from the transmission buffer (16), the data is written to the communication circuit (14) and thus output, the bus release request is cancelled, 8 bits of data is read at a time from transmission buffer (16), and the data is written into the communication circuit (14). When the transmission ready signal is provided once again, the above-described processing is repeated.
Claims4
A communication DMA device, with a CPU having a prescribed data bit width, a communication circuitry, and a memory sharing a data bus, for outputting to outside via said communication circuit transmission data connected to said memory, comprising:
- a register for storing, by control from said CPU, information indicating an area of said memory in which data to be transmitted is stored, information indicating capacity of the data to be transmitted, and information indicating start of communication;
- a bus switching requester for requesting said CPU for release of said data bus in order to allow reading of transmission data of said prescribed data bit width from said memory and for connecting said data bus to said CPU immediately after termination of the reading;
- a temporary storager for temporarily storing data read from said memory via said data bus based on the information stored in said register;
- and
- a data outputter for dividing the data of said prescribed data bit width temporarily stored in said temporary storager and outputting the data to outside via said communication circuit several bits at a time.
Dependencies are inferred from the claim text.