4 to 2 adder
AssigneeInternational Business Machines Corporation
InventorsNaoaki Aoki, Sang Hoo Dhong, Nobuo Kojima, Ohsang Kwon
Life of this patent
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Abstract
A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.
Claims10
A four-input/two-output adder comprising:
- a sum-lookahead full adder for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a first carry signal;
- and
- a modified full adder having two-levels of transistors, coupled to said sum-lookahead full adder, for receiving said first sum signal, a fourth input, and a carry signal from a backward adjacent adder to generate a second sum signal and a second carry signal.
A processor comprising:
- an instruction unit;
- and
- an execution unit coupled to said instruction unit, wherein said execution unit includes a four-input/two-output adder having
- a sum-lookahead full adder for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a first carry signal;
- and
- a modified full adder having two-levels of transistors, coupled to said sum-lookahead full adder, for receiving said first sum signal, a fourth input, and a carry signal from a backward adjacent adder to generate a second sum signal and a second carry signal.
Dependencies are inferred from the claim text.