US 6,584,484 B1 · Incorporation of split-adder logic within a carry-skip adder without additional propagation delay

Abstract

An n-bit carry-skip adder includes a number of carry-skip stages and a logic circuit associated with one or more of the stages. The logic circuit includes split-adder logic and carry-skip logic configured such that a split control signal associated with the split-adder logic is applied to at least one gate of the carry-skip logic, so as to reduce a carry propagation delay of the adder. In an illustrative embodiment, the logic circuit is associated with an (n/2+1)th carry-skip stage of the adder, and the adder is configured to perform two parallel n/2-bit additions when the split control signal is at a first logic level, and to perform a single n-bit addition when the split control signal is at a second logic level. Advantageously, the invention allows the split-adder logic to be incorporated in a manner which minimizes the carry propagation delay without increasing the required circuit area.

Claims16

Dependent claims

An adder comprising:

a plurality of carry-skip stages;
and
a logic circuit associated with at least one of the carry-skip stages, the logic circuit comprising split-adder logic and carry-skip logic, the logic circuit being configured such that a split control signal associated with the split-adder logic is applied to at least one gate of the carry-skip logic, so as to reduce a carry propagation delay of the adder.

Dependencies are inferred from the claim text.

Incorporation of split-adder logic within a carry-skip adder without additional propagation delay

Life of this patent

Incorporation of split-adder logic within a carry-skip adder without additional propagation delay

Life of this patent

Abstract

Claims16