Multiplier array processing system with enhanced utilization at lower precision
AssigneeMicroUnity Systems Engineering, Inc.
InventorsCraig C. Hansen, Henry Massalin
Life of this patent
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Abstract
A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.
Claims23
A method for performing a group-multiply-and-sum instruction, said method comprising the steps of:
- partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
- multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product;
- and
- adding each product so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
A method for performing a group-multiply-sum-and-add instruction, said method comprising the steps of:
- partitioning each of a plurality of operands into a plurality of symbols, said operands and each of said symbols having a predefined bit width;
- multiplying symbols of a first operand with symbols of a second operand, each of such multiplications producing a product;
- and
- adding each product and a third operand so as to produce a single scalar result, said scalar result capable of being represented by a bit width which is equal to or less than said predefined bit width of said operands without a reduction in the accuracy of said result.
A multiplier processing system for performing a group-convolve instruction, said system comprising:
- means for partitioning each of a plurality of operands into a plurality of symbols, said operands having a first defined bit width and said symbols having a second defined bit width, said second defined bit width being dynamically variable;
- means for multiplying a selection of symbols of a first operand with a selection of symbols of a second operand, each of such multiplications producing a selected product, said selection determined by the indices of the symbols within the first and second operand as to perform a convolution;
- and
- means for adding a plurality of selected products so as to produce a plurality of result symbols, said result symbols provided to a plurality of partitioned fields of a result operand.
A method for performing a group-multiply instruction in a general purpose, multiple precision parallel operation programmable media processor, said method comprising:
- partitioning first and second registers into a plurality of floating point operands, said floating point operands having a defined bit width, wherein said defined bit width is dynamically variable;
- multiplying, in parallel, said plurality of floating point operands in said first register by said plurality of floating point operands in said second, each of such multiplications producing a floating point product to provide a plurality of floating point products, each of said floating point products being capable of being represented by a defined bit width which is equal to said defined bit width of said operands;
- and
- providing said plurality of floating point products to a plurality of partitioned fields of a result.
A general purpose, multiple precision parallel operation programmable media processor for performing a group multiply instruction, said processor comprising:
- first and second registers partitioned into a plurality of floating point operands, said floating point operands having a defined bit width and said defined bit width being dynamically variable;
- a multiplier, configured to multiply, in parallel, said plurality of floating point operands in said first register by said plurality of floating point operands in said second register, each of such multiplications producing a floating point product to provide a plurality of floating point products, each of said floating point products being capable of being represented by a defined bit width which is equal to said defined bit width of said operands;
- and
- a result having a plurality of partitioned fields for receiving said plurality of floating point products.
Dependencies are inferred from the claim text.