Shared data and clock recovery for packetized data

A shared data and clock recovery circuit comprising:

• a clock synthesizer having a plurality of sampling signals having different phases;
• a multiple transition detector adapted to receive a data stream and said plurality of sampling signals and generate a plurality of output signals corresponding to edges detected in said data stream in response to said sampling signals;
• a counter/accumulator adapted to receive said plurality of output signals, accumulate the time differences represented by said plurality of output signals and total number of said edges detected, perform weighted average calculations to select one of said different phases, and produce an output signal;
• and
• a gain control circuit adapted to use the time differences detected by the counter/accumulator to control the progressive acquisition of lock, wherein the gain control circuit contains N number of stages progressively refining the lock position.

A shared data and clock recovery circuit comprising:

• a clock synthesizer adapted to generate a plurality of sampling signals having different phases;
• a multiple transition detector adapted to receive a packetized data stream and said plurality of sampling signals, and detect edges in said data stream in response to said sampling signals;
• a counter/accumulator adapted to detect the time occurrences and total number of said edges, perform a weighted averaging calculation, and output a signal related to said weighted averaging calculation to select one of said different phases;
• and
• a decision circuit adapted to acquire lock onto the packetized data stream, wherein the shared data and clock recovery circuit is adapted to operate using either a folded or non-folded window, wherein:
• when the shared data and clock recovery circuit is operated using a folded window, the number of bins used, amount of circuitry used, and power are reduced.

A shared data and clock recovery circuit comprising:

• a clock synthesizer having a plurality of sampling signals having different phases;
• a multiple transition detector adapted to receive a data stream and said plurality of sampling signals and generate a plurality of output signals corresponding to edges detected in said data stream in response to said sampling signals;
• a counter/accumulator adapted to receive said plurality of output signals, accumulate the time differences represented by said plurality of output signals and total number of said edges detected, and performing weighted average calculations to select one of said different phases, and produce an output signal;
• a gain control circuit adapted to use the time differences detected by the counter/accumulator to control the progressive acquisition of lock, wherein the shared data and clock recovery circuit is adapted to operate using either a folded or non-folded window;
• and
• an accumulator block adapted to take bin information from the multiple transition circuit and compute either a folded or non-folded weight.

A shared data and clock recovery circuit comprising:

• a clock synthesizer adapted to generate a plurality of sampling signals having different phases;
• a multiple transition detector adapted to receive a packetized data stream and said plurality of sampling signals, and detect edges in said data stream in response to said sampling signals;
• a counter/accumulator adapted to detect the time occurrences and total number of said edges, perform a weighted averaging calculation, and output a signal related to said weighted averaging calculation to select one of said different phases;
• a decision circuit adapted to acquire lock onto the packetized data stream;
• and
• a gain control circuit adapted to use the total number of edges detected by the counter/accumulator to control the progressive acquisition of lock, wherein the gain control circuit contains N number of stages progressively refining the lock position.

A shared data and clock recovery circuit comprising:

• a clock synthesizer having a plurality of sampling signals having different phases;
• a multiple transition detector adapted to receive a data stream and said plurality of sampling signals and generate a plurality of output signals corresponding to edges detected in said data stream in response to said sampling signals;
• a counter/accumulator adapted to receive said plurality of output signals, accumulate the time differences represented by said plurality of output signals and total number of said edges detected, and performing weighted average calculations to select one of said different phases, and produce an output signal;
• and
• a gain control circuit adapted to use the time differences detected by the counter/accumulator to control the progressive acquisition of lock, wherein the shared data and clock recovery circuit is adapted to operate using either a folded or non-folded window, wherein:
• when the shared data and clock recovery circuit is operated using a folded window, the number of bins used, amount of circuitry used, and power are reduced.