Method and apparatus sample rate conversions in an analog to digital converter

An apparatus for sample rate conversion, the apparatus comprises:

• a processing module;
• and
• memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to:
• (a) receive an input digital stream at a first clock rate;
• (b) integrate the input digital stream over multiple clock cycles at the first clock rate to produce an integrated digital signal;
• (c) determine when an interpolated digital value of the integrated digital signal is to be passed to a differentiation stage based on a difference between a sample rate conversion value and a reference value;
• (d) when the difference is within a targeted range, generate the interpolated digital value based on at least a portion of the difference and an interpolation of integration samples of the integrated digital signal occurring at cycles of the first clock rate that are temporal to when the interpolated digital value is to be passed;
• and (e) pass the interpolated digital value to the differentiation stage at a converted sample rate.

An analog to digital converter comprises:

• an oversampling quantizer operably coupled to receive an analog input signal to produce therefrom a digital data stream;
• a cascaded integrated comb filter operably coupled to receive the digital data stream and to produce therefrom a sample rate adjusted digital signal, wherein the cascaded integrated comb filter includes:
• an integration stage operably coupled to receive the digital data stream and to produce an integrated digital signal by integrating the input digital stream over multiple clock cycles of a first clock;
• a differentiation stage operably coupled to receive an interpolated sample of the integrated digital signal and to produce therefrom the sample rate adjusted digital signal;
• an interpolation stage operably coupled to receive the integrated digital signal and to produce therefrom the interpolated sample, wherein the interpolation stage includes:
• a computational module operably coupled to produce a difference value as a difference between a sample rate conversion value and a reference value, wherein the difference value is produced at cycles of the first clock;
• a comparator operably coupled to indicate when the difference value is within a target range;
• an interpolator operably coupled to produce the interpolation sample from integration samples of the integrated digital signal at cycles of the first clock when the comparator indicates that the difference value is within the target range;
• a finite impulse response filter operably coupled to receive the sample rate adjusted digital signal and to produce therefrom a digital output value.