LSI Architecture and implementation of MPEG video codec

An MPEG-compliant video processing system for both signal encoding and decoding comprising the steps of:

• processing a signal in compliance with an MPEG format to generate an encoded signal when the MPEG-compliant video processing system is operating in an encoding mode and a decoded signal when the MPEG-compliant video processing system is operating in a decoding mode;
• wherein
• if the signal is an uncompressed video data, then performing a Discrete Cosine Transform in the functional re-use DCT/IDCT module and generating an encoded signal;
• if the signal is an MPEG compressed video data, then performing an Inverse Discrete Cosine Transform in the DCT/IDCT module and generating a decoded signal;
• and
• wherein shared functional units for both signal encoding and decoding comprise a Discrete Cosine Transform/Inverse Discrete Cosine Transform (DCT/IDCT) function module, a Quantization/Inverse Quantization (QNT/IQ) function module, a Motion Compensation (MC) function module, an (SBUF) buffer module, an (MBUF) buffer module, a (CFIFO) buffer module, a (VBUF) buffer module, and a (TBUF) buffer module, and
• wherein the (SBUF) module stores and processes a reconstructed video bit stream, and the (CFIFO) module stores and processes a compressed MPEG video bit stream.

An MPEG-compliant video processing system for both signal encoding and decoding comprising the steps of:

• processing a signal in compliance with an MPEG format to generate an encoded signal when the MPEG-compliant video processing system is operating in an encoding mode and a decoded signal when the MPEG-compliant video processing system is operating in a decoding mode;
• wherein
• if the signal is an uncompressed video data, then performing a Discrete Cosine Transform in the functional re-use DCT/IDCT module;
• and generating an encoded signal;
• if the signal is an MPEG compressed video data, then performing an Inverse Discrete Cosine Transform in the DCT/IDCT module and generating a decoded signal;
• and
• wherein shared functional units for both signal encoding and decoding comprise a Discrete Cosine Transform/Inverse Discrete Cosine Transform (DCT/IDCT) function module, a Quantization/Inverse Quantization (QNT/IQ) function module, a Motion Compensation (MC) function module, an (SBUF) buffer module, an (MBUF) buffer module, a (CFIFO) buffer module, a (VBUF) buffer module, and a (TBUF) buffer module;
• and
• wherein during the encoding mode the (VBUF) module provides a signal to an adder module, and during the decoding mode the (VBUF) module provides a signal to the QNT/IQ module.