Block-mode equalization for data communications

A digital equalization method comprising:

• providing a plurality of digital bits at a first rate, each of said digital bits having a predetermined amplitude and a predetermined duration;
• converting the plurality of digital bits into a plurality of signal pulses at a second rate which is a multiple of the first rate, each of the plurality of signal pulses having an amplitude substantially greater than the predetermined amplitude and a duration substantially equal to the predetermined duration, each of the plurality of signal pulses further having a negative equalization pulse associated therewith having a magnitude greater than the predetermined magnitude and a duration of about the predetermined duration;
• and
• using the plurality of digital bits to provide a plurality of negative block equalization pulses at the first rate, each of the block equalization pulses associated with a negative equalization pulse and having a magnitude substantially less than the magnitude of the negative equalization pulse and a duration which is the multiple of the second rate over the first rate times the duration of the negative equalization pulse.

A signal equalization system comprising:

• data input circuitry receiving a plurality of digital bits and outputting a plurality of parallel signal pulses;
• data output circuitry connected to the data input circuitry to receive the plurality of parallel signal pulses and to serialize the parallel signal pulses and provide serialized signal pulses with a negative equalization pulse after each of the serialized signal pulses;
• and
• main block equalization circuitry connected to the data input circuitry to receive the plurality of parallel signal pulses and to provide a negative main block equalization pulse after each of the negative equalization pulses, the main block equalization pulse having an average magnitude of the plurality of parallel signal pulses and a duration which is the sum of the durations of the plurality of parallel signal pulses.

A digital equalization system comprising:

• input circuitry including a plurality of flip-flops having a plurality of signal outputs;
• an output multiplexer connected to the plurality of signal outputs capable of providing an amplified signal pulse followed by a negative equalization pulse;
• and
• an inverting block equalization multiplexer connected to the plurality of flip-flops capable of receiving signals therefrom, averaging the signals, and providing an inverted main block equalization pulse after the negative equalization pulse.