Method and system for accessing ports of a fixed-size cell switch

A program product, said program product being configured to execute the following steps:

• (a) splitting incoming cells over a plurality of physical units;
• (b) segmenting incoming cells into fixed-size data logical units;
• (c) generating fixed-size idle logical units, of the same size as the data logical units to fill traffic for recovering, at a receive side, a self-sampling clock for the physical units
• (d) inserting a delimiter within each idle logical unit, for cell delineation, said delimiter comprising two subfields:
• (1) a first subfield for acquiring synchronization computed only from the delimiter itself;
• and
• (2) a second subfield computed continuously on the flow of bits for further asserting and monitoring synchronization;
• and
• a computer readable media containing instructions for execution in a processor for the method and practice of said program product.

A method for operating a switch, comprising:

• (a) splitting incoming cells over a plurality of physical units;
• (b) segmenting incoming cells into fixed size data logical units;
• (c) generating fixed size idle logical units of the same size as the data logical units to fill traffic for recovering, at a receive side, a self sampling clock for the physical units;
• and
• (d) inserting a delimiter within each idle logical unit for cell delineation, said delimiter for acquiring synchronization of said self sampling clock.

A switch, comprising:

• an incoming adapter to receive incoming cells, to split said incoming cells over a plurality of physical units, to segment said incoming cells into fixed size data logical units, to generate fixed size idle logical units of the same size as the data logical units to fill traffic for recovering, at a receive side, a self sampling clock for the physical units, and said adapter inserting a delimiter within each idle logical unit for cell delineation, said delimiter for acquiring synchronization at said receive side;
• a switch fabric providing said plurality of physical units, and to switch said data logical units to an egress adapter;
• and
• said physical units synchronizing said self sampling clock to said data logical units, to said idle logical units, and to said delimiter.

A switch, comprising:

• means for splitting incoming cells over a plurality of physical units;
• means for segmenting incoming cells into fixed size data logical units;
• means for generating fixed size idle logical units of the same size as the data logical units to fill traffic for recovering, at a receive side, a self sampling clock for the physical units;
• and
• means for inserting a delimiter within each idle logical unit for cell delineation, said delimiter for acquiring synchronization of said self sampling clock.