US 6,584,121 B1 · Switch architecture for digital multiplexed signals

Abstract

In a switch in accordance with the principles of the present invention, switch modules that include a disassembly block, a switching core, and an assembly block are combined to implement an N×M multi-port switch that effectively connects N input ports to M output ports, provides broadcast capability, and may be non-blocking. The switch operates on data channels that all have their respective data blocks organized in the same number of bit-packs. Disassemblers within each module slice incoming data blocks into bit-packs and route the bit-packs to switching cores. A switching core within each module connects each input channel with each output channel at the bit-pack level. Assemblers within each module receive the switched bit-packs from each switching core and assemble the bit-packs into data blocks for each of the output channels.

Claims21

Dependent claims

A switch module for switching “Q” input data channels of digital input data to “R” output data channels, where Q and R are integers, said input data formatted as data blocks containing a fixed number of bits of data, each data block comprising “O” bit packs containing a number of bits “P”, where O and P are integers, and the fixed number of bits of data in a data block is equal to P multiplied by O, said switch module comprising:

a disassembler, for disassembling each data block into O bit packs, said disassembler configured to transmit away from a switching core PQO-PQ bits for every data block from the Q input data channels disassembled by said disassembler,
said switching core, for respectively switching bit packs from Q input data channels to R output data channels, said switching core configured to switch PQ bits for every data block from the Q input data channels disassembled by the disassembler, where PQ indicates a multiplication of P times Q;
and
an assembler, for assembling O switched bit packs, into data blocks for R output data channels.

1 more element

Dependencies are inferred from the claim text.

Switch architecture for digital multiplexed signals

Life of this patent

Switch architecture for digital multiplexed signals

Life of this patent

Abstract

Claims21