SRAM emulator
AssigneeAtmos Corporation
InventorsWlodek Kurjanowicz, Jacek Misztal
Life of this patent
Estimating the term…
Abstract
Generally, the present invention provides memory controller for providing a synchronous SRAM interface to an embedded SDRAM. To achieve maximum performance SDRAM timing, row circuitry is emulated in the controller to produce SDRAM control signals. Control signal timing is optimized for read and write operations and can be flexibly adjusted using control registers. Since the timing of DRAM control signals is based on the embedded DRAM timing emulation, all margins can be minimized and the performance of the memory can be maximized. The SRAM interface can operate in a wide range of clock frequencies, which are not restricted to ratios of multiples of the embedded DRAM clock frequency.
Claims32
An interface circuit for controlling embedded DRAM memory having a row timing circuit for activating row decoders and bitline sense amplifiers, and column decoders for accessing bitlines, comprising:
- a command decoder for receiving command signals and providing control signals in response to a system clock;
- and,
- a clock sequencer for activating the row timing circuit in response to the control signals, and for activating the column decoders at a predetermined delay after activation of the row timing circuit, the column decoders being activated after the bitline sense amplifiers are activated and within the same system clock cycle that the row timing circuit is activated.
A method for accessing a memory bank of an embedded DRAM within a single clock cycle of a system clock controlled by an interface circuit synchronized to the system clock comprising:
- a) receiving address and commands on an edge of the system clock;
- b) activating row decoders for driving a wordline of the memory bank corresponding to the address;
- c) activating bitline sense amplifiers of the memory bank;
- and,
- d) activating column decoders of the memory bank at a predetermined delay time after the row decoders are activated.
A clock sequencer of an interface circuit for controlling an embedded DRAM having column decoders, row decoders, bitline sense amplifiers and a row timing circuit for activating the row decoders and the bitline sense amplifiers comprising:
- a row timing emulator for receiving an activation clock signal synchronized to a system clock for generating an emulated row timing signal;
- a margin delay circuit for receiving the emulated row timing signal for generating a column clock signal for activating the column decoders, and a precharge clock signal;
- a page mode control circuit for receiving a page mode signal, the system clock and the activation clock signal for generating a page mode precharge clock signal;
- and,
- a clock combiner for receiving the page mode signal for activating the row timing circuit in response to one of a fast activation clock signal, the precharge clock signal, and the page mode precharge clock signal.
A method for customizing a row timing emulator and margin delay circuit of an interface circuit for controlling an embedded DRAM having a row timing circuit for activating row decoders and bitline sense amplifiers, and column decoders for accessing the bitlines comprising:
- a) determining an optimum bitline sense amplifier activation delay time for activating the bitline sense amplifiers after row addresses are latched;
- b) determining an optimum column decoder activation delay time for activating the column decoders after the bitline sense amplifiers are activated;
- c) programming delay elements of the row timing circuit for activating the bitline sense amplifiers at the optimum bitline sense amplifier activation delay time;
- d) programming delay elements of the row timing emulator for generating an emulated row timing signal at the optimum bitline sense amplifier activation time;
- and,
- e) programming delay elements of the margin delay circuit for activating the column decoders at the optimum column decoder activation delay time after receiving the emulated row timing signal.
Dependencies are inferred from the claim text.