Supply noise reduction in memory device column selection

A column select circuit having a pass transistor and further having a driver circuit coupled to supply a gate bias to a gate of the pass transistor, wherein the driver circuit comprises:

• an output coupled to the gate of the pass transistor;
• an unfiltered path having a first potential node coupled to receive a first supply potential, and a first field-effect transistor interposed between the first potential node and the output;
• and
• a filtered path having a second potential node coupled to receive a second supply potential, a second field-effect transistor interposed between the second potential node and the output, and an RC filter interposed between the second potential node and the second field-effect transistor;
• wherein the driver circuit is responsive to a first control signal and a second control signal such that the first field-effect transistor is activated when the first control signal has a first logic level and the second control signal has a first logic level, the first field-effect transistor is deactivated when the first control signal has a second logic level and the second control signal has its first logic level, and the first field-effect transistor and the second field-effect transistor are deactivated when the second control signal has a second logic level regardless of a logic level of the first control signal.

A column select circuit having a pass transistor and further having a driver circuit coupled to supply a gate bias to a gate of the pass transistor, wherein the driver circuit comprises:

• an output coupled to the gate of the pass transistor;
• a first supply potential node;
• a second supply potential node;
• a first ground potential node;
• a second ground potential node;
• a first field-effect transistor having a first source/drain region coupled to the first supply potential node and a second source/drain region coupled to the output;
• a second field-effect transistor having a first source/drain region and having a second source/drain region coupled to the output;
• a third field-effect transistor having a first source/drain region coupled to the output and a second source/drain region coupled to the first ground potential node;
• a resistive component interposed between the first source/drain region of the second field-effect transistor and the second supply potential node;
• and
• a capacitive component interposed between the first source/drain region of the second field-effect transistor and the second ground potential node;
• wherein the driver circuit is responsive to a first control signal having a first or second logic level and a second control signal having a first or second logic level such that the first field-effect transistor is activated only when the first control signal has its first logic level and the second control signal has its first logic level, the second field-effect transistor is activated only when the second control signal has its first logic level regardless of a logic level of the first control signal, and the third field-effect transistor is activated only when the second control signal has its second logic level regardless of a logic level of the first control signal.

A method of operating a memory device, comprising:

• deactivating a pass transistor during a non-sensing phase to isolate a target memory cell from a sensing device;
• activating the pass transistor during a first sensing phase to permit coupling of the target memory cell to the sensing device, wherein activating the pass transistor during the first sensing phase comprises coupling a gate of the pass transistor to a first potential node;
• activating the pass transistor during a second sensing phase to permit coupling of the target memory cell to the sensing device, wherein activating the pass transistor during the second sensing phase comprises coupling the gate of the pass transistor to a second potential node through a filtered path and isolating the gate of the pass transistor from the first potential node;
• and
• sensing a programmed state of the target memory cell during the second sensing phase, while the gate of the pass transistor is coupled to the second potential node through the filtered path and while the gate of the pass transistor is isolated from the first potential node.

A method of operating a memory device, comprising:

• deactivating a pass transistor during a non-sensing phase to isolate a target memory cell from a sensing device;
• activating the pass transistor during a first sensing phase to permit coupling of the target memory cell to the sensing device, wherein activating the pass transistor during the first sensing phase comprises coupling a gate of the pass transistor to a first potential node through an unfiltered path and to a second potential node through a filtered path;
• activating the pass transistor during a second sensing phase to permit coupling of the target memory cell to the sensing device, wherein activating the pass transistor during the second sensing phase comprises isolating the gate of the pass transistor from the first potential node while the gate of the pass transistor remains coupled to the second potential node through the filtered path;
• and
• sensing a programmed state of the target memory cell during the second sensing phase, while the gate of the pass transistor is coupled to the second potential node through the filtered path and while the gate of the pass transistor is isolated from the first potential node.

A memory device including a column select circuit having a pass transistor and further having a driver circuit coupled to supply a gate bias to a gate of the pass transistor, wherein the driver circuit comprises:

• an output coupled to the gate of the pass transistor;
• an unfiltered path having a first potential node coupled to receive a first supply potential, and a first field-effect transistor interposed between the first potential node and the output;
• and
• a filtered path having a second potential node coupled to receive a second supply potential, and a second field-effect transistor interposed between the second potential node and the output;
• wherein the driver circuit has a first state to couple the gate of the pass transistor to the second potential node through the filtered path and to isolate the gate of the pass transistor from the first potential node;
• wherein the driver has a second state to couple the gate of the pass transistor to at least the first potential node through the unfiltered path;
• and
• wherein the driver has a third state to isolate the gate of the pass transistor from both the first potential node and the second potential node.

An electronic system having a memory device coupled to a processor, wherein the memory device includes a column select circuit having a pass transistor and further having a driver circuit coupled to supply a gate bias to a gate of the pass transistor, wherein the driver circuit comprises:

• an output coupled to the gate of the pass transistor;
• an unfiltered path having a first potential node coupled to receive a first supply potential, and a first field-effect transistor interposed between the first potential node and the output;
• and
• a filtered path having a second potential node coupled to receive a second supply potential, and a second field-effect transistor interposed between the second potential node and the output;
• wherein the driver circuit has a first state to couple the gate of the pass transistor to the second potential node through the filtered path and to isolate the gate of the pass transistor from the first potential node;
• wherein the driver has a second state to couple the gate of the pass transistor to at least the first potential node through the unfiltered path;
• and
• wherein the driver has a third state to isolate the gate of the pass transistor from both the first potential node and the second potential node.