Flash memory array structure suitable for multiple simultaneous operations
AssigneeAplus Flash Technology, Inc.
InventorsFu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
Life of this patent
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Abstract
In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.
Claims11
A memory for simultaneous memory operations, comprising:
- a) a memory array,
- b) a plurality of multi-port sector decoders,
- c) a plurality of groups of main bit lines,
- d) said memory array organized into a plurality of sectors, each of said sectors comprising a plurality of columns of memory cells connected to a plurality of sub bit lines,
- e) a sector decoder of said plurality of multi-port sector decoders coupled to each sector of said plurality of sectors and selecting which group of main bit lines to couple to said sub bit lines.
Dependencies are inferred from the claim text.