US 6,584,031 B2Granted

Semiconductor integrated circuit device

AssigneesHitachi, Ltd., Hitachi Device Engineering Co., Ltd.

InventorsHiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana

Life of this patent

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Abstract

In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.

Claims3

Dependent claims

A semiconductor integrated circuit comprising:

a charge pump circuit;
a detection circuit which detects a level of an output voltage of said charge pump circuit;
and
an oscillation circuit which is controlled on the basis of said detection circuit and outputs a signal to said charge pump circuit,
wherein said charge pump circuit operates on a first voltage and comprises a first transistor with a gate insulation film having a first thickness,
wherein said oscillation circuit operates on a second voltage lower than said first voltage and comprises a second transistor with a gate insulation film having a second thickness which is smaller than said first thickness, and
wherein said detection circuit operates on said second voltage and comprises a third transistor with a gate insulation film having said first thickness.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/107,139Filed 28 Mar 2002 · continuation
Priority: JP 10-1143179 Apr 1998
Published: US 2002/0097628 A125 Jul 2002
Granted: 24 Jun 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification2 codes

G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C
Static stores

Family

Application09/288,512Parent of this division · filed 8 Apr 1999
Application09/742,078Parent of this continuation · filed 22 Dec 2000
Application09/907,929Parent of this continuation · filed 19 Jul 2001
US 2002/0097628 A1Pre-grant publication · published 25 Jul 2002
US 6,385,118 B2Parent of this continuation
US 6,288,967 B1Parent of this continuation
Application09/742,078Parent of this division
US 6,195,305 B1Parent of this division
US 2001/0000691 A1Published application
US 2001/0040835 A1Published application
US 6,584,031 B2This patent

From the US filing history. Foreign family members aren’t listed.