Memory circuit regulation system and method

A SRAM regulation system, comprising:

• an array regulator adapted for distributing an array supply voltage to a SRAM cell array that includes a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• a bias generator for offsetting parasitic leakage currents in each of the plurality of LL4TCMOS SRAM cells by controlling a subthreshold current from one of the complementary bit lines through a pass transistor;
• and
• at least one periphery regulator adapted for distributing a periphery supply voltage to at least one periphery circuit.

A SRAM regulation system, comprising:

• an array regulator adapted for distributing an array supply voltage to a SRAM cell array that includes a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• and
• at least one periphery regulator adapted for distributing a periphery supply voltage to at least one periphery circuit,
• wherein the array supply voltage is within the range of 1.0V to 1.5V and the at least one periphery supply voltage is within the range of 0.7V to 1.2V.

A memory device, comprising:

• a memory cell array;
• at least one periphery circuit coupled to the memory cell array;
• an array regulator coupled to the memory cell array and adapted for distributing an array supply voltage to the memory cell array;
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit;
• and
• a bias generator coupled to the array regulator, wherein the array regulator is coupled to bit line loads in the memory array and the bias generator is coupled to local row drivers, and the bias generator is adapted to control current from bit lines to the memory cell array to offset leakage current in the memory cell array.

A memory device, comprising:

• a memory cell array;
• at least one periphery circuit coupled to the memory cell array;
• an array regulator coupled to the memory cell array and adapted for distributing an array supply voltage to the memory cell array;
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit;
• a bias generator coupled to the array regulator, wherein the array regulator is coupled to bit line loads in the memory array and the bias generator is coupled to local row drivers, wherein the bias generator provides a temperature-dependent bias voltage.

A memory device, comprising:

• a memory cell array including a plurality of memory cells, wherein each memory cell within the memory cell array has a stable margin of failure;
• at least one periphery circuit, wherein the at least one peripheral circuit has a stable margin of failure;
• an array regulator coupled to the memory cell array and adapted for distributing an array supply voltage to the memory cell array;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit.

A memory device, comprising:

• a memory cell array having a lower array operation voltage level for which level the memory cell array maintains a stability margin;
• at least one periphery circuit having a lower periphery operation voltage level for which level the at least one periphery circuit maintains a stability margin;
• an array regulator coupled to the memory cell array and adapted for distributing an array supply voltage to the memory cell array, wherein the array supply voltage is above the lower array operation voltage level;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit, wherein the at least one periphery supply voltage is above the lower periphery operation voltage level.

A memory device, comprising:

• a memory cell array including a plurality of transistors arranged in an array transistor circuit, wherein the array transistor circuit has an array threshold voltage;
• at least one periphery circuit including a plurality of transistors arranged in a periphery transistor circuit, wherein the periphery transistor circuit has a periphery threshold voltage;
• an array regulator coupled to the memory cell array and adapted for distributing an array supply voltage to the memory cell array, wherein the array supply voltage provides a stable margin of failure over the array threshold voltage;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit, wherein the at least one periphery supply voltage provides a stable margin of failure over the periphery threshold voltage.

A SRAM device, comprising:

• a SRAM cell array, including a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• at least one periphery circuit coupled to the SRAM cell array;
• an array regulator coupled to the SRAM cell array and adapted for distributing an array supply voltage to the SRAM cell array through the complementary digit lines;
• a bias generator to control a number of pass transistors to source current from a number of the digit lines to offset parasitic leakage currents in the SRAM cell array;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit.

A SRAM device, comprising:

• a SRAM cell array, including a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• at least one periphery circuit coupled to the SRAM cell array;
• an array regulator coupled to the SRAM cell array and adapted for distributing an array supply voltage to the SRAM cell array through the complementary digit lines;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit, wherein the array supply voltage is within the range of 1.0V to 1.5V and the at least one periphery supply voltage is within the range of 0.7V to 1.2V.

A SRAM device, comprising:

• a SRAM cell array, including a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• at least one periphery circuit coupled to the SRAM cell array;
• an array regulator coupled to the SRAM cell array and adapted for distributing an array supply voltage to the SRAM cell array through the complementary digit lines;
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit;
• and
• a bias generator coupled to the array regulator, wherein the array regulator is coupled to bit line loads in the memory array and wherein the bias generator is coupled to local row drivers, wherein the bias generator provides a temperature-dependent bias voltage.

An electronic system, comprising:

• a processor;
• and
• a memory device operably coupled to the processor wherein the memory device comprises:
• a memory cell array;
• at least one periphery circuit coup led to the memory cell array;
• an array regulator coupled to the memory cell array and adapted for distributing an array supply voltage to the memory cell array;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing at least one periphery supply voltage to the at least one periphery circuit;
• and
• a bias generator coupled to the array regulator, wherein the bias generator is adapted to control current from bit lines to the memory cell array to offset leakage current in the memory cell array.

An electronic system, comprising:

• a processor;
• and
• a SRAM device operably coupled to the processor wherein the SRAM comprises:
• a SRAM cell array, including a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• at least one periphery circuit coupled to the SRAM cell array;
• an array regulator coupled to the SRAM cell array and adapted for distributing an array supply voltage to the SRAM cell array through the complementary digit lines;
• a bias generator to control a number of pass transistors to source current from a number of the digit lines to offset parasitic leakage currents in the SRAM cell array;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing a periphery supply voltage to the at least one periphery circuit.

An electronic system, comprising:

• a processor;
• and
• a SRAM device operably coupled to the processor wherein the SRAM comprises:
• a SRAM cell array, including a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• at least one periphery circuit coupled to the SRAM cell array;
• an array regulator coupled to the SRAM cell array and adapted for distributing an array supply voltage to the SRAM cell array through the complementary digit lines;
• and
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing a periphery supply voltage to the at least one periphery circuit,
• wherein the array supply voltage is within the range of 1.0V to 1.5V and the at least one periphery supply voltage is within the range of 0.7V and 1.2V.

An electronic system, comprising:

• a processor;
• and
• a SRAM device operably coupled to the processor wherein the SRAM comprises:
• a SRAM cell array, including a plurality of LL4TCMOS SRAM cells, each of the plurality of LL4TCMOS SRAM cells being connected to a word line and to complementary digit lines;
• at least one periphery circuit coupled to the SRAM cell array;
• an array regulator coupled to the SRAM cell array and adapted for distributing an array supply voltage to the SRAM cell array through the complementary digit lines;
• at least one periphery regulator coupled to the at least one periphery circuit and adapted for distributing a periphery supply voltage to the at least one periphery circuit;
• and
• a bias generator coupled to the array regulator, wherein the bias generator provides a temperature dependent bias voltage.

A method of providing regulated power to a memory circuit, comprising:

• providing at least one periphery voltage level from at least one periphery regulator to at least one periphery circuit;
• providing an array voltage level from an array regulator to a memory array;
• and
• providing a subthreshold bit line current to offset leakage current in the memory array.

A method of forming a memory circuit regulation system, comprising:

• providing at least one periphery regulator;
• coupling the at least one periphery regulator to at least one periphery circuit;
• providing at least one array regulator;
• providing a word line bias generator;
• coupling the array regulator to bit line loads in the memory array;
• coupling the array regulator to the word line bias generator;
• and
• coupling the word line bias generator to local row drivers in the memory array such that the word line bias generator controls a gate voltage for a number of pass transistors to provide a subthreshold bit line current to offset leakage current in the memory array.

A method of forming a memory device, comprising:

• providing at least one periphery regulator;
• providing at least one periphery circuit;
• coupling the at least one periphery regulator to at least one periphery circuit;
• providing an array regulator;
• providing a memory array;
• coupling the array regulator to a memory array;
• providing a word line bias generator;
• coupling the array regulator to bit line loads in the memory array;
• coupling the array regulator to the word line bias generator;
• and
• coupling the word line bias generator to local row drivers in the memory array such that the word line bias generator controls a gate voltage for a number of pass transistors to provide a subthreshold bit line current to offset leakage current in the memory array.