Semiconductor integrated circuit capable of adjusting input offset voltage

A semiconductor integrated circuit comprising:

• first and second transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
• third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
• a fifth transistor connected between a connection point of said respective drain terminals of said first and second transistors and a first data line;
• a sixth transistor connected between a connection point of said respective drain terminals of said third and fourth transistors and a second data line;
• and
• an offset supply circuit configured to supply an offset voltage to at least one of said first and second data lines before turning on said fifth and sixth transistors to cancel out an input offset voltage of said semiconductor integrated circuit,
• wherein said connection point of said respective drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to a connection point of the respective drain terminals of said third and fourth transistors.

A semiconductor integrated circuit comprising:

• first and second transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
• third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to the other drain terminal;
• a fifth transistor connected between a connection point of said respective drain terminals of said first and second transistors and a first data line;
• a sixth transistor connected between a connection point of said respective drain terminals of said third and fourth transistors and a second data line;
• a seventh transistor connected between said respective gate terminals of said first and second transistors and said first data line;
• and
• an eighth transistor connected between said respective gate terminals of said third and fourth transistors and said second data line,
• wherein said connection point of said respective drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to said respective drain terminals of said third and fourth transistors.

A semiconductor integrated circuit comprising:

• first and second transistors each having one source terminal being connected to a drain terminal of the other one of said first and second transistors;
• third and fourth transistors each having one source terminal being connected to a drain terminal of the other one of said third and fourth transistors;
• and
• a voltage supply circuit configured to counterchange a voltage to be supplied to the drain terminals of said first and third transistors and a voltage to be supplied to the source terminals of said second and fourth transistors depending on whether valid data is supplied to first and second data lines,
• wherein said first data line is connected to gate terminals of said first and fourth transistors,
• said second data line being connected to gate terminals of said second and third transistors, and
• said first to fourth transistors shifting a level of data of said first and second data lines with a predetermined timing.

A semiconductor integrated circuit comprising:

• first and second transistors each having one source terminal being connected to a drain terminal of the other one of said first and second transistors;
• third and fourth transistors each having one source terminal being connected to a drain terminal of the other one of said third and fourth transistors;
• a fifth transistor connected between the source terminals of said second and fourth transistors and a first voltage terminal;
• a sixth transistor connected between the drain terminals of said first and third transistors and a second voltage terminal;
• a seventh transistor connected between the drain terminals of said first and third transistors and said first voltage terminal;
• and
• an eighth transistor connected between the source terminals of said second and fourth transistors and said second voltage terminal,
• wherein a first data line is connected to gate terminals of said first and fourth transistors, and a second data line is connected to gate terminals of said second and third transistors.

A semiconductor integrated circuit comprising:

• first and second transistors each having one source terminal being connected to a drain terminal of the other one of said first and second transistors;
• third and fourth transistors each having one source terminal being connected to a drain terminal of the other one of said third and fourth transistors;
• a fifth transistor connected between said source terminals of said second and fourth transistors and a first voltage terminal;
• a sixth transistor connected between said drain terminals of said first and third transistors and a second voltage terminal;
• a seventh transistor connected between said source terminals of said second and fourth transistors and said second voltage terminal;
• an eighth transistor having a gate terminal being connected to a gate terminal of said first transistor and having a drain terminal being connected to said source terminal of said first transistor and a gate terminal of said third transistor;
• a ninth transistor having a gate terminal being connected to said gate terminal of said third transistor and having a drain terminal being connected to said source terminal of said third transistor and said gate terminal of said first transistor;
• and
• a tenth transistor connected between source terminals of said eighth and ninth transistors and said first voltage terminal,
• wherein a first data line is connected to a gate terminal of said second transistor and a second data line is connected to a gate terminal of said fourth transistor.

A semiconductor integrated circuit comprising:

• two input nodes forming a pair;
• two output nodes configured to output amplification signals in accordance with a difference in signals inputted to said two input nodes;
• at least a pair of internal nodes of signal paths from said input nodes to said output nodes;
• and
• a latch circuit configured to hold a signal inputted from outside said semiconductor integrated circuit, and
• an input offset adjustment circuit which is connected to any of said input nodes, said internal nodes and said output nodes and controls an input offset voltage of said semiconductor integrated circuit in accordance with data held in said latch circuit.

A semiconductor integrated circuit comprising:

• first and second transistors having gate terminals being connected to each other and one drain terminal being connected to a drain terminal of the other one of said first and second transistors;
• third and fourth transistors having gate terminals being connected to each other and one drain terminal being connected to a drain terminal of the other one of said first and second transistors;
• a fifth transistor connected between a connection point of said drain terminals of said first and second transistors and a first data line;
• a sixth transistor connected between a connection point of said drain terminals of said third and fourth transistors and a second data line;
• a first voltage setting circuit capable of further strongly (further weakly) holding low-level voltages of said gate terminals of said first and second transistors;
• and
• a second voltage setting circuit capable of further strongly (further weakly) holding low-level voltage of said gate terminals of said third and fourth transistors,
• wherein said connection point of said drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to said connection point of said drain terminals of said third and fourth transistors.

A semiconductor integrated circuit comprising:

• first and second transistors having gate terminals being connected to each other and one drain terminal being connected to a drain terminal of the other one of said first and second transistors;
• third and fourth transistors having gate terminals connected to each other and one drain terminal being connected to a drain terminal of the other one of said first and second transistors;
• a fifth transistor connected between a connection point of said drain terminals of said first and second transistors and a first data line;
• a sixth transistor connected between a connection point of said drain terminals of said third and fourth transistors and a second data line;
• a first voltage setting circuit capable of further strongly (further weakly) holding high-level voltages of said gate terminals of said first and second transistors;
• and
• a second voltage setting circuit capable of further strongly (further weakly) holding high-level voltages of said gate terminals of said third and fourth transistors,
• wherein said connection point of said drain terminals of said first and second transistors is connected to said respective gate terminals of said third and fourth transistors, and said respective gate terminals of said first and second transistors are connected to said connection point of said drain terminals of said third and fourth transistors.