Read compression in a memory
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Dean Nobunaga
Life of this patent
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Abstract
A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.
Claims11
A non-volatile flash memory device comprising:
- an array of non-volatile memory cells;
- a plurality of data output buffers to provide data from the array to external nodes;
- control circuitry to select between compressed output data and un-compressed output data;
- and
- first and second data paths between the array and the plurality of data output buffers, wherein the control circuitry can select the first data path that comprises compression logic to compress the data from the array.
A non-volatile flash memory device comprising:
- an array of non-volatile memory cells arranged in rows and columns;
- a plurality of output buffers;
- first and second compression circuitry wherein the first compression circuitry has a 4 to 1 compression ratio to compress 16 data bits from the array to 4 output buffers;
- and
- control circuitry to select the first and/or the second compression circuitry to output compressed data via the plurality of output buffers.
A method of operating a memory array comprising:
- initiating a test operation;
- selecting either a compressed data path or an un-compressed data path;
- and
- coupling data from the memory array to output connections through the selected data path.
A method of operating a non-volatile flash memory comprising:
- receiving test instructions, including externally provided signals received on data output connections;
- initiating a test operation in response to the test instructions;
- selecting either a first compression circuit having a 4 to 1 compression ratio or second compression circuit having a 16 to 1 compression ratio;
- and
- coupling data from the array to output connections through the selected compression circuit to provide compressed output test data.
An electronic system comprising:
- a processor that generates control signals;
- and
- a memory device that receives the control signals, the memory device comprising:
- an array of non-volatile memory cells;
- a plurality of data output buffers to provide data from the array to external nodes;
- control circuitry to select between compressed output data and un-compressed output data in response to the control signals;
- and
- first and second data paths between the array and the plurality of data output buffers, wherein the control circuitry can select the first data path that comprises compression logic to compress the data from the array.
Dependencies are inferred from the claim text.