Semiconductor memory device with simultaneous data line selection and shift redundancy selection
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTakaharu Tsuji
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Abstract
The semiconductor memory device includes a memory cell array, a normal data line pair, a redundant data line pair and a data line switch circuit. The data line switch circuit includes an IO shift decoder decoding the column address and the position information related to a defective data line, and an IO select unit shifting the connection between a data input/output pin and a data line while replacing the defective data line according to the decoded result. High speed data transfer is realized by carrying out simultaneously data line selection and redundancy selection according to the column address.
Claims18
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix;
- a plurality of data lines including a redundant data line and a normal data line to read out data from said memory cell array or write data into said memory cell array;
- a plurality of external data lines to transfer data with an external source;
- and
- a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with said plurality of external data lines and a shift operation of shifting connection between said plurality of external data lines and said data line to be coupled according to an external address and data line information related to a defective data line in said normal data line.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix;
- a plurality of data lines including a redundant data line and a normal data line to read out data from said memory cell array or write data into said memory cell array;
- a plurality of external data lines to transfer data with an external source;
- and
- a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with said plurality of external data lines according to an external address and a replacement operation of replacing a defective data line in said data line to be coupled with said redundant data line according to data line information related to the defective data line included in said normal data line.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix;
- a plurality of data lines including a redundant data line and a normal data line to read out data from said memory cell array or writing data into said memory cell array;
- a plurality of external data lines to transfer data with an external source;
- and
- a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with an external data line to be used according to a bus width and a shift operation of shifting connection between said external data line to be used and said data line to be coupled according to data line information related to a defective data line in said normal data line.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix;
- a plurality of data lines including first and second redundant data lines and a plurality of normal data lines to read out data from said memory cell array or write data into said memory cell array;
- a plurality of external data lines to transfer data with an external source, provided corresponding to said plurality of normal data lines, respectively, and
- a data line switch circuit executing simultaneously a select operation of selecting a data line to be coupled with an external data line that is to be used and a shift operation of shifting connection between said external data line to be used and said data line to be coupled according to data line information related to a defective data line in said plurality of data lines.
Dependencies are inferred from the claim text.