Semiconductor memory device having intermediate voltage generating circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTadaaki Yamauchi, Makoto Muneyasu
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Abstract
In a bit line reference potential (VBL) generating circuit, a pad is connected via a transfer gate to a reference node in a reference stage. During a device evaluation test, the transfer gate is turned on in response to a test signal so that a voltage is applied to the reference node with a tester driver via the pad to control a potential of an output node in an output stage. Thus, the semiconductor memory device is capable of stably controlling the bit line reference potential VBL regardless of the drivability of the tester driver during the device evaluation test.
Claims8
A semiconductor memory device capable of conducting a device evaluation test, comprising:
- a memory cell array including a plurality of memory cells;
- and
- an intermediate voltage generating circuit for generating an intermediate voltage to be supplied to said memory cell array, wherein
- said intermediate voltage generating circuit includes
- an output stage including a first transistor connected between an output node and a power-supply node and a second transistor connected between said output node and a ground node,
- a reference stage including a first reference voltage generating circuit connected between a reference node and a power-supply node for generating a first reference voltage that is higher than a voltage of said reference node and that is to be supplied to a control electrode of said first transistor and a second reference voltage generating circuit connected between said reference node and a ground node for generating a second reference voltage that is lower than a voltage of said reference node and that is to be supplied to a control electrode of said second transistor, and
- a pad connected to said reference node for receiving a voltage externally supplied during said device evaluation test.
Dependencies are inferred from the claim text.