Nonvolatile memory structures and access methods
AssigneeMosel Vitelic, Inc.
InventorsHsing T. Tuan, Li-Chun Li, Vei-Han Chan
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Abstract
In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.
Claims8
A method for accessing a nonvolatile memory which has a plurality of rows of nonvolatile memory cells, each memory cell having a first semiconductor region, a first gate for controlling a conductivity of the first semiconductor region, a second gate insulated from the first gate, and a first source/drain region through which a current flows to or from the first semiconductor region, the method comprising:
- driving the first gates of each row being accessed into a first state, the second gates of each row being accessed into a second state, and the first source/drain regions of each row being accessed into a third state;
- driving the first gates of the rows not being accessed into a state or states different from the first state, the first gates thus selecting a row or rows being accessed;
- for some row R1 being accessed and some rows R2, R3 which are not being accessed, driving the second gates of the row R2 into the second state, driving the first source/drain regions of the row R3 into the third state, and driving the second gates of the row R3 into a state or states different from the second state, such that:
- (i) the second gates of the rows R1, R2 are in the same, second, state, (ii) the first source/drain regions of the rows R1, R3 are in the same, third, state but (iii) the second gates of the rows R1, R3 are not in the same state.
Dependencies are inferred from the claim text.