Electrically alterable non-volatile memory with N-bits per cell

An electrically alterable non-volatile multi-level memory device, comprising:

• a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a memory FET having a storage structure, electrons being capable of being injected into the storage structure from a drain-source current path in each of the plurality of non-volatile multi-level memory cells, and
• wherein operations of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells selectively among a plurality of states including at least a first state, a second state, a third state and a fourth state are carried out in accordance with information to be stored in the one non-volatile multi-level memory cell,
• wherein programming reference values for programming the first, second and third states are generated, and read reference values, which are different from the programming reference values, for reading the first, second and third states are generated,
• wherein operations of verifying programming of the one non-volatile multi-level memory cell among the first, second and third states are carried out and include comparing the parameter of the one non-volatile multi-level memory cell with the programming reference values, each operation of setting the parameter to a selected one of the first, second and third states being conducted until it is verified that the parameter of the one non-volatile multi-level memory cell has been set to the selected state,
• wherein operations of reading the one non-volatile multi-level memory cell are carried out using the read reference values to evaluate the parameter of the non-volatile multi-level memory cell,
• wherein the read reference values are values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits,
• wherein the normal read operation includes evaluating the parameter of the one non-volatile multi-level memory cell with a sense circuit using the read reference values, and
• wherein the plurality of non-volatile multi-level memory cells are arranged in a matrix of rows and columns disposed in substantially a rectangle that has a first side, a second side, a third side and a fourth side, the first side and the second side intersect with each other substantially perpendicularly, a plurality of word lines coupled with gate electrodes of memory FET's of the multi-level memory cells and the first side of the rectangle intersect with each other substantially perpendicularly, a plurality of bit lines coupled with drain-source current paths of memory FET's of the multi-level memory cells and the second side of the rectangle intersect with each other substantially perpendicularly, a row select circuit is disposed at the first side of the rectangle for coupling with the plurality of word lines, and peripheral circuitry, including a column select circuit and the sense circuit, is disposed at the second side of the rectangle.