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US 6,584,011 B2Granted
Magnetic random access memory
AssigneeKabushiki Kaisha Toshiba
InventorKentaro Watanabe
Life of this patent
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Abstract
A semiconductor integrated circuit device comprises a plurality of magnetic tunneling junction elements, a writing word line which provides an auxiliary magnetic field for writing data to the plurality of magnetic tunneling junction elements, a plurality of bit lines connected to ones of ends of the respective plurality of magnetic tunneling junction elements, and a cell selecting transistor. The cell selecting transistor is commonly connected to other ends of the respective plurality of magnetic tunneling junction elements.
Claims15
A semiconductor integrated circuit device comprising:
- a plurality of magnetic tunneling junction elements;
- a writing word line which applies an auxiliary magnetic field for writing data to the plurality of magnetic tunneling junction elements;
- a plurality of bit lines connected to ones of ends of the respective plurality of magnetic tunneling junction elements;
- a cell selecting transistor commonly connected to other ends of the respective plurality of magnetic tunneling junction elements;
- and
- a selecting word line which drives the cell selecting transistor.
3 more elements
Dependencies are inferred from the claim text.