Selective device coupling
AssigneeMicron Technology, Inc.
InventorJeff A. McClain
Life of this patent
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Abstract
Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conductance or non-conductance. When the selective isolation device is in a state of conductance, the first capacitor is coupled to the second capacitor. When the selective isolation device is in a state of non-conductance, the first capacitor is electrically isolated from the second capacitor. In memory devices, such parallel coupling of adjacent storage capacitors of adjacent memory cells is useful in increasing beta ratio and providing defect isolation. Such coupling of adjacent storage capacitors generally reduces the number of uniquely addressable memory cells.
Claims31
A method of operating a memory device, comprising:
- coupling a first storage capacitor of a first mommy cell to a second storage capacitor of a second memory cell during a first period in response to a control signal received;
- coupling the first storage capacitor to a digit line during the first period;
- electrically isolating the first storage capacitor of the first memory cell from the second storage capacitor of the second memory cell during a second period;
- and
- coupling the first storage capacitor to the digit line during the second period.
A method of operating a memory device, comprising:
- establishing a coupled capacitor pair in a first period from a first storage capacitor of a first memory cell and a second storage capacitor of a second memory cell and coupling the capacitor pair to a digit line in response to a control signal received;
- and
- decoupling the coupled capacitor pair in a second period isolating the first capacitor and the second capacitor from each other.
A method of operating a memory device, comprising:
- receiving a control signal in a first period;
- and
- dynamically forming a coupled capacitor pair from a first storage capacitor of a first memory cell and a second storage capacitor of a second memory cell in response to the control signal and coupling the capacitor pair to a digit line during the first period.
A method of operating a memory device, comprising:
- receiving a control signal initiated by a user during a first period;
- and
- creating a coupled capacitor pair by coupling a first storage capacitor of a first memory cell to a second storage capacitor of a second memory cell and coupling the capacitor pair to a digit line in response to the signal during the first period.
A method of operating a memory device, comprising:
- coupling adjacent storage capacitors having adjacent memory cells during a first period in response to a control signal received, wherein the storage capacitors are in a first state;
- and
- coupling the adjacent storage capacitors to a digit line during the first period.
A method of operating a memory device, comprising:
- activating a coupled capacitor pair during a first period in response to a control signal received, wherein the capacitor pair includes a first storage capacitor of a first memory cell and a second storage capacitor of a second memory cell;
- and
- placing the coupled capacitor pair in communication with a single digit line during the first period.
A method of operating a memory device, comprising:
- detecting and isolating a first storage capacitor of a first memory cell from an adjacent second storage capacitor of a second memory cell during a first period in response to a control signal received;
- and
- statically coupling the capacitors during a second period to a digit line permitting the coupled capacitors to operate as a single storage capacitor.
A method of operating a memory device, comprising:
- isolating a coupled capacitor pair formed from a first storage capacitor of a first memory cell and a second storage capacitor of a second memory cell during a first period in response to a control signal received;
- and
- coupling the first capacitor to a digit line.
A method of operating a memory device, comprising:
- accessing a first memory cell of a first storage capacitor coupled to a digit line during a first period in response to a control signal received;
- and
- concurrently accessing a second memory coil of a second storage capacitor and the first memory cell during a second period.
A method of operating a memory device, comprising:
- identifying a first state change during a first period and in response to the first state change forming a coupled capacitor pair from a first storage capacitor of a first memory cell and a second storage capacitor of a second memory cell in response to a control signal received;
- coupling the coupled capacitor pair to a digit line during the first period;
- identifying a second state change during a second period and in response to the second state change isolating the first storage capacitor from the second storage capacitor;
- and
- coupling the first storage capacitor to the digit line during the second period.
Dependencies are inferred from the claim text.