Memory integrated circuit with improved reliability
AssigneesInfineon Technologies AG, Kabushiki Kaisha Toshiba
InventorsThomas Roehr, Hans-Oliver Joachim
Life of this patent
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Abstract
A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.
Claims15
A method of operating a memory IC in which memory cells are grouped in chains comprising:
- maintaining wordlines of the memory IC at a first logic 1 voltage level during stand by mode;
- increasing the wordlines to a second logic 1 voltage level in preparation for a memory access, wherein the second logic 1 voltage level is higher than the first logic 1 voltage level;
- and
- driving one of the wordlines associated with a selected memory cell to a logic 0.
Dependencies are inferred from the claim text.