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US 6,584,008 B2Granted
Ferroelectric non-volatile memory device including a layered structure formed on a substrate
AssigneeSemiconductor Technology Academic Research Center
InventorHiroshi Ishiwara
Life of this patent
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Abstract
A ferroelectric non-volatile memory device comprising a MOS cell transistor, two ferroelectric capacitors each of which has one terminal connected to the gate electrode of the cell transistor and has almost the same remanent polarization, and a selector transistor connected to the other terminal of one ferroelectric capacitor, wherein data is stored by polarizing the ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor.
Claims9
A ferroelectric non-volatile memory device comprising:
- a cell transistor constituted by an n-channel MOS transistor having a p-type silicon substrate, a pair of first n-type diffusion regions formed in the p-type silicon substrate, and a gate electrode placed, with an insulating intermediate layer, over the p-type silicon substrate between the first n-type diffusion regions;
- a selector transistor which is adjacent to said cell transistor, and is constituted by an n-channel MOS transistor having a pair of second n-type diffusion regions formed in the p-type substrate, and a second gate electrode placed, with an insulating intermediate layer, over the p-type silicon substrate between the second n-type diffusion regions;
- and
- two capacitors formed of a ferroelectric film formed on the gate electrode of said cell transistor, and two capacitor electrodes formed on said ferroelectric film and formed of ferroelectric thin films, wherein one of said capacitors is connected to one of the second n-type diffusion regions of said selector transistor and the capacitor electrodes are electrically separated from the first n-type diffusion regions of the cell transistor.
1 more element
A ferroelectric non-volatile memory device comprising:
- a cell transistor constituted by an n-channel MOS transistor having a p-type silicon substrate, a pair of first n-type diffusion regions formed in the p-type silicon substrate, and a gate electrode placed, with an insulating intermediate layer, over the p-type silicon substrate between the first n-type diffusion regions;
- a selector transistor which is adjacent to the cell transistor, and is constituted by an n-channel MOS transistor having a pair of second n-type diffusion regions formed in the p-type substrate, and a second gate electrode placed, with an insulating intermediate layer, over the p-type silicon substrate between the second n-type diffusion regions;
- two capacitors formed of a ferroelectric film formed on the gate electrode of the cell transistor, and two capacitor electrodes formed on the ferroelectric film and formed of ferroelectric thin films, wherein one of the capacitors is connected to one of the second n-type diffusion regions of the selector transistor;
- a plate line connected to the capacitor electrode of the other of the capacitors;
- a word line connected to the second gate electrode of the selector transistor;
- and
- a bit line connected to the other of the second n-type diffusion regions of the selector transistor;
- wherein the first n-type diffusion regions of the cell transistor are respectively grounded and connected to the word line.
5 more elements
Dependencies are inferred from the claim text.