Circuit and method for testing a ferroelectric memory device
AssigneeSTMicroelectronics S.r.l.
InventorDavid C. McClure
Life of this patent
Estimating the term…
Abstract
A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.
Claims38
A random access memory device, comprising:
- a memory array of memory cells organized into rows and columns, including a plurality of word lines and column lines, each row of memory cells being coupled to a word line and each column of memory cells being coupled to a column line;
- sense amplifier circuitry coupled to the column lines;
- address decode circuitry for receiving an address value and asserting a row line associated therewith;
- and
- test circuitry, coupled to the column lines, for selectively sensing voltage levels appearing on the column lines and providing externally to the random access memory device an electrical signal representative of the sensed voltage levels.
A method of testing a semiconductor memory device having an array of memory cells, comprising:
- sensing voltage levels appearing in the memory cells;
- converting the sensed voltage levels into current levels that are proportional to the sensed voltage levels;
- and
- providing externally to the semiconductor memory device electrical signals representative of the sensed voltage levels, the electrical signals being the current levels to which the sensed voltage levels are converted.
A method of testing a semiconductor memory device having an array of memory cells, comprising:
- sensing voltage levels appearing in the memory cells;
- converting the voltage levels sensed into current levels;
- sequentially applying each of the current levels to a capacitor;
- and
- for each current level, providing externally to the semiconductor memory device an electrical signal representative of the voltage level appearing on the capacitor.
An integrated circuit, comprising:
- a memory device, comprising:
- a memory cell;
- and
- test circuitry for selectively measuring a voltage level maintained in the memory cell and providing the measurement externally to the integrated circuit, the test circuitry measures the voltage level maintained in the memory cell and provides externally to the integrated circuit an electrical signal representative of the measured voltage level, the test circuitry comprises a current mirror having a first current leg coupled to the memory cell and a second current leg coupled to an output of the integrated circuit.
An integrated circuit, comprising:
- a memory device, comprising:
- a memory cell;
- and
- test circuitry for selectively measuring a voltage level maintained in the memory cell and providing the measurement externally to the integrated circuit, wherein the memory cell is a ferroelectric memory cell.
Dependencies are inferred from the claim text.