MRAM bit line word line architecture
AssigneeInfineon Technologies North America Corp.
InventorHans-Heinrich Viehmann
Life of this patent
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Abstract
A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device.
Claims20
A memory device comprising:
- a plurality of bit lines;
- a plurality of word lines, the plurality of word lines forming a cross-point array with the plurality of bit lines;
- a plurality of memory cells, whereby one of the plurality of memory cells is located at each of the cross-points in the array;
- a bit decoder coupled to the bit lines, the bit decoder having current sources and current sinks coupled to the bit lines;
- a word decoder coupled to the word lines, the word decoder having current sources and current sinks coupled to the word lines;
- and
- a first series of switch circuits coupled to two adjacent bit lines, the first series of switch circuits located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines;
- whereby the memory cell at the corresponding cross-point is selected for writing when the corresponding bit and word lines are provided with a programming current.
A method of selecting a memory cell in a cross-point array having a plurality of conductive lines, the array having switch circuits located along two adjacent conductive lines resulting in segments of the two adjacent conductive lines, the method comprising:
- selecting a memory cell for writing, the memory cell coupled to one of the two adjacent conductive lines in an associated segment;
- programming the switch circuits whereby the one of two adjacent conductive lines in the associated segment receives a programming current and a other of the two adjacent conductive lines in the associated segment receives no programming current;
- and
- programming the switch circuits whereby the two adjacent conductive lines in the other segments each receive a portion of the programming current.
Dependencies are inferred from the claim text.