Semiconductor memory device preventing erroneous writing in write operation and delay in read operation

A semiconductor memory device, comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• a plurality of word lines provided corresponding to the memory cell rows and selectively activated;
• and
• a plurality of bit lines provided on opposite sides of each of the memory cell columns so as to extend in a column direction, each bit line being shared by adjacent two memory cell columns, wherein
• each of said memory cells of each of said memory cell rows is electrically coupled between adjacent two bit lines,
• said semiconductor memory device further comprising:
• a bit-line control section for controlling setting of a voltage of said plurality of bit lines in write operation and read operation, wherein
• said bit-line control section divides said plurality of bit lines into first and second groups based on a selected memory cell column, and sets the bit lines of said first group to one of first and second voltages and sets the bit lines of said second group to the other of said first and second voltages.