Subranging analog to digital converter with multi-phase clock timing

An N-bit analog to digital converter comprising:

• a reference ladder;
• a track-and-hold amplifier tracking an input voltage;
• a two-phase clock having phases φ1 and φ2;
• a plurality of coarse ADC amplifiers each connected to a corresponding coarse capacitor at its input, wherein the coarse ADC amplifiers are reset on φ1 and their corresponding coarse capacitors are connected to an output of the track-and-hold on φ2, and wherein the track-and-hold amplifier is in a hold-mode on φ2;
• a plurality of fine ADC amplifiers each connected to a corresponding fine capacitor at its input, wherein the fine ADC amplifiers are reset on φ2 and their corresponding fine capacitors are charged to the track-and-hold amplifier output voltage on φ2;
• a switch matrix that selects a voltage subrange from the reference ladder, based on outputs of the coarse ADC amplifiers, for input to the fine ADC amplifiers on φ1;
• and
• an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

An N-bit analog to digital converter comprising:

• a reference ladder;
• a track-and-hold amplifier tracking an input voltage;
• a two-phase clock having phases φ1 and φ2;
• a coarse capacitor connected to the track-and-hold amplifier on φ2 and to the reference ladder on φ1;
• a coarse ADC amplifier that resets on φ1 and amplifies a voltage on the coarse capacitor on φ2;
• a coarse comparator for latching an output of the coarse ADC amplifier on φ1+1 cycle;
• a fine capacitor connected to the track-and-hold on φ2 and to a fine voltage tap of the reference ladder on φ1, the fine voltage tap selected based on the output of the coarse ADC amplifier, wherein the track-and-hold amplifier is in a hold-mode on φ2;
• a fine ADC amplifier including a plurality of cascaded amplifier stages,
• wherein a first cascaded amplifier stage resets on φ2 and amplifies a voltage on the fine capacitor on φ1+1cycle, a second cascaded amplifier stage resets on φ1+1cycle and amplifies the voltage on the fine capacitor on φ2+1 cycle, a third cascaded amplifier stage resets on φ2+1cycle and amplifies the voltage on the fine capacitor on φ1+2 cycles, and so on;
• a fine comparator for latching an output of a last cascaded amplifier stage;
• and
• an encoder converting outputs of the coarse and fine comparators to an N-bit output.

An N-bit analog to digital converter comprising:

• a reference ladder;
• a track-and-hold amplifier tracking an input voltage;
• a two-phase clock having alternating phases φ1 and φ2;
• a plurality of coarse capacitors connected to an output of the track-and-hold on φ2 and to corresponding coarse taps of the reference ladder on φ1;
• a plurality of coarse ADC amplifiers that reset on φ1 and amplify voltages on the coarse capacitors on φ2;
• a plurality of coarse comparators for latching outputs of the coarse ADC amplifiers;
• a plurality of fine capacitors connected to the output of track-and-hold amplifier on φ2 and connected to fine voltage taps of the reference ladder on φ1, the fine voltage taps selected based on the outputs of the coarse ADC amplifiers, wherein the track-and-hold amplifier is in a hold-mode on φ2;
• a plurality of fine ADC amplifiers, each including a plurality of cascaded amplifier stages,
• wherein the cascaded amplifier stages reset and amplify on alternating phases φ1 and φ2,
• wherein amplifiers of the first stage are reset on φ2 and amplify voltages of the fine capacitors on φ1;
• a plurality of fine comparators for latching outputs of a last amplifier stage;
• and
• an encoder converting outputs of the coarse and fine comparators to an N-bit output.

An N-bit analog to digital converter comprising:

• a two-phase clock having phases φ1 and φ2;
• a reference ladder;
• a track-and-hold amplifier tracking an input voltage;
• a coarse ADC amplifier that resets on φ1 and amplifies a difference of an output of the track-and-hold amplifier and a coarse tap of the reference ladder on φ2, wherein the track-and-hold amplifier is in a hold-mode on φ2;
• a fine ADC amplifier that resets on φ2 and amplifies a difference of the output of the track-and-hold amplifier and a fine tap of the reference ladder on φ1;
• a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier;
• and
• an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

A method of converting analog to digital voltage comprising the steps of:

• resetting a coarse ADC amplifier on the first clock phase;
• charging a coarse capacitor to a first reference voltage during a first clock phase of a two phase clock;
• connecting the coarse capacitor to an input voltage during a second clock phase of the two phase clock;
• wherein the T/H amplifier is in hold-mode during the 2nd clock phase;
• selecting the second reference voltage based on an output of the coarse ADC amplifier;
• connecting a fine capacitor to a second reference voltage during the first clock phase;
• charging the fine capacitor to the input voltage during the second clock phase;
• amplifying a voltage on the coarse capacitor on the second clock phase;
• resetting a fine ADC amplifier on the second clock phase;
• amplifying a voltage of the fine capacitor on the first clock phase;
• and
• converting outputs of the coarse and fine ADC amplifiers to an N-bit output.

A method of converting analog to digital voltage comprising the steps of:

• on a first clock phase, charging a coarse capacitor to a first reference voltage, connecting a fine capacitor to a second reference voltage, resetting a coarse ADC amplifier, and amplifying a voltage of the fine capacitor;
• on a second clock phase, connecting the coarse capacitor to an output of a track-and-hold amplifier, setting the track-and-hold amplifier to a hold mode, charging the fine capacitor to the input voltage, resetting a fine ADC amplifier, selecting a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier;
• and
• converting outputs of the coarse and fine ADC amplifiers to an N-bit output.