High frequency CMOS differential amplifiers with fully compensated linear-in-dB variable gain characteristic

A high frequency CMOS differential amplifier, comprising:

• a high frequency variable gain amplifier for providing a differential variable gain amplification of a first and a second input signal, where the gain of said high frequency variable gain amplifier depends on a first and a second bias current applied to said high frequency variable gain amplifier, said high frequency variable gain amplifier comprising at least two differential amplifiers, where the gain of said high frequency variable gain amplifier is independent of temperature and process;
• a bias control circuit for receiving an intermediate control voltage, a second control voltage, and a biasing current and producing said first and said second bias current by comparing said intermediate control voltage against reference voltages, where said reference voltages are generated by said bias control circuit from said second control voltage and a first operational amplifier;
• a gain-slope correction circuit for receiving a first control voltage, said second control voltage, a temperature independent first reference current, and a proportional to absolute temperature (PTAT) dependent current and producing said intermediate control voltage as a function of temperature by comparing said temperature independent first reference current and said PTAT dependent current, thereby compensating for a change in slope of the gain control characteristics with temperature of said high frequency variable gain amplifier, said gain-slope correction circuit further comprising:
• a gain-slope correction comparator used to comparing said temperature independent first reference current with said PTAT dependent current and digitizing the comparison, said gain-slope correction comparator further comprising:
• a series of current comparators formed with p-channel cascoded and n-channel cascoded transistors serially coupled, where the gates of said p-channel cascoded transistors are driven by a voltage drop generated by said first reference current across a first gain-slope correction resistive means, and where the gates of said n-channel cascoded transistors are driven by a voltage drop generated by said PTAT current across a second gain-slope correction resistive means, a junction of said p-channel cascoded and n-channel cascoded transistor going more positive when said p-channel cascoded transistor carries a higher current than its serially coupled n-channel cascoded transistor;
• a decoder coupled to the junctions of said p-channel cascoded and n-channel cascoded transistors for receiving digitized signals from said junctions thus providing digital logic signal outputs ranging from all “zeros” to all “ones”;
• a feedback ratio circuit for altering the feedback ratio and thus the amplification-attenuation of a second operational amplifier with temperature, said feedback ratio circuit further comprising:
• a series of control switches, equal in number to the number of outputs from said decoder, activated by said logic signal outputs, where one terminal of all of said control switches is ganged together into one line;
• said second operational amplifier for receiving at its negative input said ganged together line, and for receiving at its positive input said second control voltage;
• a serially coupled string of temperature control resistive means, numbering one more than the number of logic signal outputs of said decoder, coupled between said first control voltage and the output of said second operational amplifier, where the other terminal of said first control switch is coupled between the first and the second temperature control resistive means, where the other terminal of said second control switch is coupled between the second and the third temperature control resistive means, and so on, till the other terminal of said last control switch is coupled between the next-to-last and last temperature control resistive means;
• a temperature sensing circuit for providing said band-gap reference voltage plus proportional to absolute temperature (PTAT) dependent current generator, and said temperature independent first and second reference current;
• and
• a gain compensation circuit for receiving said temperature independent second reference current, and said biasing current, which is modified to correct the temperature/process dependency of said variable gain amplifier.

A high frequency CMOS differential amplifier, comprising:

• a high frequency variable gain amplifier for providing a differential variable gain amplification of a first and a second input signal, where the gain of said high frequency variable gain amplifier depends on a first and a second bias current applied to said high frequency variable gain amplifier, said high frequency variable gain amplifier comprising at least two differential amplifiers, where the gain of said high frequency variable gain amplifier is independent of temperature and process;
• a bias control circuit for receiving an intermediate control voltage, a second control voltage, and a biasing current and producing said first and said second bias current by comparing said intermediate control voltage against reference voltages, where said reference voltages are generated by said bias control circuit from said second control voltage and a first operational amplifier;
• a gain-slope correction circuit for receiving a first control voltage, said second control voltage, a temperature independent first reference current, and a proportional to absolute temperature (PTAT) dependent current and producing said intermediate control voltage as a function of temperature by comparing said temperature independent first reference current and said PTAT dependent current, thereby compensating for a change in slope of the gain control characteristics with temperature of said high frequency variable gain amplifier, said gain-slope correction circuit further comprising:
• a gain-slope correction comparator used to comparing said temperature independent first reference current with said PTAT dependent current and digitizing the comparison, said gain-slope correction comparator further comprising:
• a series of current comparators formed with p-channel cascoded and n-channel cascoded transistors serially coupled, where the gates of said p-channel cascoded transistors are driven by a voltage drop generated by said first reference current across a first gain-slope correction resistive means, and where the gates of said n-channel cascoded transistors are driven by a voltage drop generated by said PTAT current across a second gain-slope correction resistive means, a junction of said p-channel cascoded and n-channel cascoded transistor going more positive when said p-channel cascoded transistor carries a higher current than its serially coupled n-channel cascoded transistor;
• a decoder coupled to the junctions of said p-channel cascoded and n-channel cascoded transistors for receiving digitized signals from said junctions thus providing digital logic signal outputs ranging from all “zeros” to all “ones”;
• a feedback ratio circuit for altering the feedback ratio and thus the amplification-attenuation of a second operational amplifier with temperature, said feedback ratio circuit further comprising:
• a series of control switches, equal in number to the number of outputs from said decoder, activated by said logic signal outputs, where one terminal of all of said control switches is ganged together into one line;
• said second operational amplifier for receiving at its negative input said ganged together line, and for receiving at its positive input said second control voltage;
• a serially coupled string of temperature control resistive means, numbering one more than the number of logic signal outputs of said decoder, coupled between said first control voltage and the output of said second operational amplifier, where the other terminal of said first control switch is coupled between the first and the second temperature control resistive means, where the other terminal of said second control switch is coupled between the second and the third temperature control resistive means, and so on, till the other terminal of said last control switch is coupled between the next-to-last and last temperature control resistive means;
• a temperature sensing circuit for providing said band-gap reference voltage plus proportional to absolute temperature (PTAT) dependent current generator, and a temperature independent first and second reference current, said temperature sensing circuit further comprising:
• a band-gap reference-cum-PTAT current generator for generating a temperature independent band-gap voltage node of about 1.2 volt, and for providing said PTAT dependent current which increases linearly with temperature;
• a temperature-to-current converter (TTC) for converting said band-gap voltage into a nearly temperature independent prime current reference IREF, and for splitting said prime current reference IREF into said first and said second reference current, said TTC further comprising:
• a third operational amplifier having a negative and a positive input, and an output, the positive input of said third operational amplifier coupled to said 1.2 volt bandgap voltage node;
• a first and a second voltage-to-current converter (VTCC) MOS transistor, the gates of said first and said second VTCC MOS transistor coupled to the output of said third operational amplifier, the source said first and said second VTCC coupled to the negative input of said third operational amplifier to provide feedback, the source said first and said second VTCC additionally in communication with a reference potential via a prime reference resistive means, where the drain of said first VTCC MOS transistor provides said prime current reference IREF, and where the drain of said second VTCC MOS transistor is the current source for said second bias current;
• and
• a gain compensation circuit for receiving said temperature independent second reference current, and said biasing current which is modified by said temperature independent second reference current.