Reduced clock-skew in a multi-output clock driver by selective shorting together of clock pre-outputs

A reduced-skew clock driver comprising:

• a clock input;
• a plurality of cells, each cell receiving an enable signal and the clock input and outputting a clock output, each cell comprising:
• pre-driver means, receiving the clock input and the enable signal, for driving high and low in response to the clock input an intermediate output when the enable signal is in an enabling state, and for driving a constant voltage onto the intermediate output when the enable signal is not in the enabling state;
• and
• output buffer means, receiving the intermediate output from the pre-driver means, for buffering the intermediate output to drive the clock output;
• shorting means, receiving a first enable signal to a first cell and a second enable signal to a second cell in the plurality of cells, for shorting the intermediate output in the first cell to the intermediate output in the second cell when the first and second enable signals are both in the enabling state, and for isolating the intermediate output in the first cell from the intermediate output in the second cell when the first and second enable signals are in different states,
• whereby intermediate outputs are shorted to reduce skew when cells for two intermediate outputs are both enabled.

A skew-reduced multi-output buffer comprising:

• a data input;
• a first enable input;
• a second enable input;
• a third enable input;
• a first pre-driver, receiving the data input and the first enable input, outputting a first pull-up pre-driver line and a first pull-down pre-driver line;
• a first pull-up transistor with a gate that receives the first pull-up pre-driver line, a source coupled to a power supply, and a drain that drives a first data output;
• a first pull-down transistor with a gate that receives the first pull-down pre-driver line, a source coupled to a ground, and a drain that drives the first data output;
• a second pre-driver, receiving the data input and the second enable input, outputting a second pull-up pre-driver line and a second pull-down pre-driver line;
• a second pull-up transistor with a gate that receives the second pull-up pre-driver line, a source coupled to the power supply, and a drain that drives a second data output;
• a second pull-down transistor with a gate that receives the second pull-down pre-driver line, a source coupled to the ground, and a drain that drives the second data output;
• a third pre-driver, receiving the data input and the third enable input, outputting a third pull-up pre-driver line and a third pull-down pre-driver line;
• a third pull-up transistor with a gate that receives the third pull-up pre-driver line, a source coupled to the power supply, and a drain that drives a third data output;
• a third pull-down transistor with a gate that receives the third pull-down pre-driver line, a source coupled to the ground, and a drain that drives the third data output;
• first shorting logic, receiving the first and second enable inputs, for activating a first short signal when the first and second enable inputs are both in an enabling state that cause the first and second pre-drivers to buffer the data input to the first and second pre-driver outputs;
• a first pull-up shorting transistor, receiving the first short signal at a gate, for conducting current between the first pull-up pre-driver line and the second pull-up pre-driver line when the first short signal is activated;
• a first pull-down shorting transistor, receiving the first short signal at a gate, for conducting current between the first pull-down pre-driver line and the second pull-down pre-driver line when the first short signal is activated;
• second shorting logic, receiving the second and third enable inputs, for activating a second short signal when the second and third enable inputs are both in an enabling state that cause the second and third pre-drivers to buffer the data input to the second and third pre-driver outputs;
• a second pull-up shorting transistor, receiving the second short signal at a gate, for conducting current between the second pull-up pre-driver line and the third pull-up pre-driver line when the second short signal is activated;
• and
• a second pull-down shorting transistor, receiving the second short signal at a gate, for conducting current between the second pull-down pre-driver line and the third pull-down pre-driver line when the second short signal is activated,
• whereby timing skews between the first, second, and third data outputs are minimized by shorting the pre-driver lines.