US 6,583,657 B1Granted

Single-edge clock adjustment circuits for PLL-compatible, dynamic duty-cycle correction circuits

AssigneeInternational Business Machines Corporation

InventorsJames Patrick Eckhardt, Byron Lee Krauter

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Abstract

A duty cycle correction circuit is configured to adjust the duty cycle of a clock signal in a clock distribution network. The duty cycle correction circuit adjusts the duty cycle of the clock signal by adjusting the transitional delay in a single edge of each clock pulse of the clock signal without interrupting the other edge of each clock pulse of the clock signal. This feature enables the duty cycle correction circuit to adjust the duty cycle of the clock signal without interrupting the operation of a phase-locked loop (PLL) used in the clock distribution network. The duty cycle correction circuit includes a delay-control circuit coupled to a clock-inverter circuit. The delay-control circuit generates a delay-control voltage, which is provided to the clock-inverter circuit to control the transitional delay in a single edge of each clock pulse of the clock signal.

Claims19

Dependent claims

A duty cycle correction circuit comprising:

a delay-control circuit configured to receive a first clock signal and generate a delay-control voltage, wherein the first clock signal consists of a train of clock pulses, each of which clock pulses has a rising clock edge and a falling clock edge, the delay-control circuit including:
a first voltage divider configured to receive the first clock signal and generate a first output voltage representing a dc average of the first clock signal;
a second voltage divider configured to generate a second output voltage;
a differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the first voltage divider to receive the first output voltage, wherein the second input terminal is coupled to the second voltage divider to receive the second output voltage, and wherein the output terminal outputs a third output voltage;
and
a stability circuit coupled to the output terminal to receive the third output voltage and generate the delay-control voltage by stabilizing the third output voltage;
and
a clock-inverter circuit configured to receive a second clock signal and the delay-control voltage and to generate a third clock signal, wherein the clock-inverter circuit is biased with first and second bias voltages, the clock-inverter circuit including:
a first field effect transistor (FET) having a source, a gate, and a drain, wherein the gate of the first FET is coupled to the delay-control voltage, and wherein the source of the first FET is coupled to the first bias voltage;
a second FET having a source, a gate, and a drain, wherein the source of the second FET is coupled to the first bias voltage, wherein the gate of the second FET receives the second clock signal, and wherein the drain of the second FET outputs the third clock signal;
a third FET having a source, a gate, and a drain, wherein the source of the third FET is coupled to the drain of the first FET, wherein the gate of the third FET is coupled to the gate of the second FET, and wherein the drain of the third FET is coupled to the drain of the second FET;
and
a fourth FET having a source, a gate, and a drain, wherein the source of the fourth FET is coupled to the second bias voltage, wherein the gate of the fourth FET is coupled to the gates of the second and third FETs, and wherein the drain of the fourth FET is coupled to the drains of the second and third FETs.

10 more elements

A duty cycle correction circuit comprising:

a delay-control circuit configured to receive a first clock signal and generate a delay-control voltage, wherein the first clock signal consists of a train of clock pulses, each of which clock pulses has a rising clock edge and a falling clock edge, the delay-control circuit including:
a first voltage divider configured to receive the first clock signal and generate a first output voltage representing a dc average of the first clock signal;
a second voltage divider configured to generate a second output voltage;
a differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is coupled to the first voltage divider to receive the first output voltage, wherein the second input terminal is coupled to the second voltage divider to receive the second output voltage, and wherein the output terminal outputs a third output voltage;
and
a stability circuit coupled to the output terminal to receive the third output voltage and generate the delay-control voltage by stabilizing the third output voltage;
and
a clock-inverter circuit configured to receive a second clock signal and the delay-control voltage and to generate a third clock signal, wherein the clock-inverter circuit is biased with first and second bias voltages, the clock-inverter circuit including:
a first field effect transistor (FET) having a source, a gate, and a drain, wherein the gate of the first FET is coupled to the delay-control voltage, and wherein the source of the first FET is coupled to the first bias voltage;
a second FET having a source, a gate, and a drain, wherein the source of the second FET is coupled to the first bias voltage;
a third FET having a source, a gate, and a drain, wherein the source of the third FET is coupled to the drain of the first FET, wherein the gate of the third FET is coupled to the gate of the second FET, and wherein the drain of the third FET is coupled to the drain of the second FET;
a fourth FET having a source, a gate, and a drain, wherein the source of the fourth FET is coupled to the second bias voltage, wherein the gate of the fourth FET is coupled to the gates of the second and third FETs, and wherein the drain of the fourth FET is coupled to the drains of the second and third FETs;
a first transistor inverter having fifth and sixth FETs, the fifth and sixth FETs each having a source, a gate, and a drain, wherein the source of the fifth FET is coupled to the second bias voltage, wherein the source of the sixth FET is coupled to the first bias voltage, wherein the drain of the fifth FET is coupled to the drain of the sixth FET, wherein the gates of the fifth and sixth FETs are coupled together to receive the second clock signal, and wherein the drain of the fifth FET is coupled to the gates of the second, third, and fourth FETs;
and
a second transistor inverter having seventh and eighth FETs, the seventh and eighth FETs each having a source, a gate, and a drain, wherein the source of the seventh FET is coupled to the second bias voltage, wherein the source of the eighth FET is coupled to the first bias voltage, wherein the drain of the seventh FET is coupled to the drain of the eighth FET, wherein the gates of the seventh and eighth FETs are coupled together to the drain of the fourth FET, and wherein the drain of the seventh FET is configured to output the third clock signal.

12 more elements

Dependencies are inferred from the claim text.