Differential clock driver with transmission-gate feedback to reduce voltage-crossing sensitivity to input skew

A differential output buffer comprising:

• true initial pull-up means, responsive to a true initial gate that receives a complement differential input signal, for driving a true differential output high;
• true final pull-up means, responsive to a true final gate that receives a delayed complement differential input signal, for driving the true differential output high;
• first feedback means, coupled between a gate of the true final pull-up means and a complement differential output, for sharing charge among the gate of the true final pull-up means and the complement differential output;
• complement initial pull-up means, responsive to a complement initial gate that receives a true differential input signal, for driving the complement differential output high;
• complement final pull-up means, responsive to a complement final gate that receives a delayed true differential input signal, for driving the complement differential output high;
• second feedback means, coupled between a gate of the complement final pull-up means and the true differential output, for sharing charge among the gate of the complement final pull-up means and the true differential output;
• true initial pull-down means, responsive to a true initial gate that receives a complement differential input signal, for driving a true differential output high;
• true final pull-down means, responsive to a true final gate that receives a delayed complement differential input signal, for driving the true differential output high;
• third feedback means, coupled between a gate of the true final pull-down means and a complement differential output, for sharing charge among the gate of the true final pull-down means and the complement differential output;
• complement initial pull-down means, responsive to a complement initial gate that receives a true differential input signal, for driving the complement differential output high;
• complement final pull-down means, responsive to a complement final gate that receives a delayed true differential input signal, for driving the complement differential output high;
• and
• fourth feedback means, coupled between a gate of the complement final pull-down means and the true differential output, for sharing charge among the gate of the complement final pull-down means and the true differential output.

A differential clock driver comprising:

• a first transistor having a drain connected to a first output node and a gate coupled to a first gate node;
• a second transistor having a drain connected to the first output node and a gate coupled to a second gate node;
• a first resistor coupled between the first gate node and the second gate node;
• a first pass transistor having a source coupled to the second gate node and a drain coupled to a second output node;
• a third transistor having a drain connected to the second output node and a gate coupled to a third gate node;
• a fourth transistor having a drain connected to the second output node and a gate coupled to a fourth gate node;
• a second resistor coupled between the third gate node and the fourth gate node;
• a second pass transistor having a source coupled to the third gate node and a drain coupled to the first output node;
• wherein the first output node and the second output node are differential outputs driven to opposite states during signaling;
• wherein the first gate node and the third gate node are differential nodes driven to opposite states during signaling.