Clock control circuit

A clock control circuit comprising:

• a ring counter, in which counting direction is changed over based upon an up signal and a down-signal input thereto, for outputting, as the count value thereof, 2N(where N is a integer not less than 2)-number of bit patterns of N-bit signals and outputting N-bit inverted signals obtained by inverting each bit of the N-bit signals;
• the rescue circuit, which receives a 2N-bit signals comprising the N-bit signal and the N-bit inverted signal output from said ring counter, for determining whether the 2N-bit signals are a bit pattern that is outside expectations and, when a bit pattern that is outside expectations is detected, for replacing the bit pattern with an allowed bit pattern;
• a flag generating circuit for generating a flag signal that takes on a first logic value or a seconds logic value in dependence upon the bit pattern of the 2N-bit signals output from said ring counter;
• a decoder circuit, which receives an output signal output from the rescue circuit, for outputting a decoded signal in which at least two adjacent bits among the 2N bits take on a first value and the other bits take on a second value, the 2Nth bit and the first bit at the ends of the 2N-bit signal being adjacent;
• a clock selector, which receives a plurality of clock signals of equally spaced phase differences and which receives the decoded signal of 2N bits output from said decoder circuit as a clock selection control signal, for outputting a pair of clock signals selected from among the 2N-number of clock signals;
• an interpolator, which receives from first and second input terminals, the pair of clock signals output from the clock selector, for outputting, from an output terminal, a clock signal having a delay time corresponding to a time obtained by internally dividing a phase difference between the pair of clock signals at an interior-division ratio set by an interior-division control signal input thereto;
• a phase comparator circuit for receiving the clock signal output from said interpolator, and a reference clock and for comparing the phase of the clock signal and the phase of the reference clock;
• and
• an interpolator control circuit, which receives a phase-comparison result signal output from said phase comparator circuit and the flag signal output from said flag generating circuit, and which comprises a shift register, the shift direction of which is varied based upon values of these signals, for supplying said interpolator with the interior-division control signal that sets the interior-division ratio of said interpolator.

A clock control circuit comprising:

• a ring counter circuit, outputting 2N-bit(where N is a integer not less than 2) width signals made up of N-bit signals which is the count value thereof, and N-bit inverted signals, each bit of which is complementary signal of each bit of the N-bit signals of the count value;
• the decoder circuit, which receives a 2N-bit width signals output from said ring counter, for inverting one bit of the 2N-bit signals to thereby output a decoded signal in which at least two adjacent bits among the 2N bits take on a first value and the other bits take on a second value, the 2Nth bit and the first bit at the ends of the 2N-bit signals being adjacent;
• a clock selector, which receives a plurality of clock signals of shifted phases and which receives the decoded signal output from said decoder circuit as a clock selection control signal, for outputting a pair of clock signals selected from the plurality of clock signals;
• an interpolator, which receives from first and second input terminals the pair of clock signals output from said clock selector, for outputting a clock signal having a delay time corresponding to a time obtained by internally dividing a phase difference between the pair of clock signals at an interior-division ratio set by an interior-division control signal provided thereto;
• a phase comparator circuit for comparing the phase of the clock signal, output from said interpolator, and the phase of a reference clock;
• and
• an interpolator control circuit, which receives a phase-comparison result signal output from said phase comparator circuit, and for supplying said interpolator with the interior-division control signal that sets the interior-division ratio of said interpolator,
• counting direction of said ring counter being changed over between up and down directions based on the phase-comparison result signal output from said phase comparator circuit.