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US 6,583,653 B1Granted
Method and apparatus for generating a clock signal
AssigneeIntel Corporation
InventorPhilip W. Doberenz
Life of this patent
Estimating the term…
Abstract
In accordance with one embodiment of the invention a circuit includes a split delay-chain, a phase detector, and a voltage controlled oscillator (VCO) coupled so as to produce a clock signal based on a non-external reference.
Claims22
A device comprising:
- a split delay-chain;
- a phase detector;
- and
- a voltage controlled oscillator (VCO);
- said split delay-chain, phase detector and VCO being coupled together to form a clock circuit.
2 more elements
A method of adjusting a clock signal comprising:
- propagating a delayed version of the clock signal,
- comparing a phase relationship of the clock signal with the delayed version,
- clearing the delayed version so as to result in a reduced duty cycle for the delayed version, and
- adjusting the clock signal frequency based, at least in part, on the phase relationship.
1 more element
A clock circuit comprising:
- a split delay-chain, a phase detector, and a voltage controlled oscillator (VCO) being coupled so as to produce a clock signal based, at least in part, on a non-external reference signal.
A component comprising:
- a split delay-chain ;
- and
- a phase detector;
- said split delay-chain and phase detector being coupled so as to compare a phase relationship of two oscillating signals to be applied to said split delay-chain and said phase detector.
1 more element
Dependencies are inferred from the claim text.