Latching annihilation based logic gate

A precharge circuit for a microprocessor comprising:

• a logic section having one or more inputs and a first precharged node that is charged high during a precharge state and in response to a transition to an evaluate state remains high with a unique combination of the one or more inputs, and discharges low for the other one or more input combinations;
• a screening device operably connected to the logic section, the screening device having a second precharged node with a value in the evaluate state that is based on the first precharged node when the circuit transitions to the evaluate state;
• an output whose value is based on the value of the second precharged node, whereby the value of the output is based on the one or more inputs when the circuit transitions from the precharge to the evaluate state;
• and
• a first clamping device for clamping the screening device off after the circuit transitions to the evaluate state.

A precharge circuit comprising:

• a logic section having one or more inputs and a first precharged node that is charged high during a precharge state and in response to a transition to an evaluate state remains high with a unique combination of the one or more inputs, and discharges low for the other one or more input combinations;
• a screening device operably connected to the logic section, the screening device having a second precharged node with a value in the evaluate state that is based on the first precharged node when the circuit transitions to the evaluate state;
• an output whose value is based on the value of the second precharged node, whereby the value of the output is based on the one or more inputs when the circuit transitions from the precharge to the evaluate state;
• a first latching device for latching the second precharge node at its correct logical value in response to the transition, wherein the latching device maintains the low correct value in the evaluate state without regard to the one or more inputs;
• and
• a second latching device for latching the first precharge node to a low value when it is low in response to the transition.