Method and apparatus for fine granularity clock gating
AssigneeIntel Corporation
InventorZhong-Ning (George) Cai
Life of this patent
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Abstract
A method and apparatus provide power control for a multiple giga-hertz frequency integrated circuit. The method and apparatus include multiple levels of clock gating control circuitry and a clock distribution network to generate a low-skew system clock signal, and generate a gated clock signal, from the system clock signal, and distribute the gated clock signal to a plurality of local logic circuits in the integrated circuit.
Claims23
A clock distribution apparatus, comprising:
- a clock source;
- a plurality of local logic circuits;
- a clock distribution network interconnecting the clock source to each of the local logic circuits, the network including a plurality of clock gating control circuits;
- and
- a clock gating control circuit provided in a propagation path between the clock source and each of the local logic circuits, wherein the control system is to respond to a clock gating condition to initiate a clock gating enabling signal for at least one clock gating control circuit.
A clock distribution apparatus, comprising:
- a clock source;
- a plurality of local logic circuits;
- a clock distribution network interconnecting the clock source to each of the local logic circuits, the network including a plurality of clock gating control circuits;
- and
- a clock gating control circuit provided in a propagation path between the clock source and each of the local logic circuits,
- wherein the control system is to respond to a clock gating condition to initiate a clock gating enabling signal for at least one clock gating control circuit, and
- wherein said clock gating condition includes a combination of global, interface, and local clock gating conditions.
An apparatus to control power consumption for an integrated circuit, comprising:
- a clock distribution network to generate at least one clock signal for an integrated circuit;
- and
- a multiple level clock gating control circuit including at least a high-level clock gating control circuit and a low-level clock gating control circuit to generate, without redundant input of enabling signals for clock gating, a gated clock signal from the clock signal, and distribute the gated clock signal to one of a plurality of local logic circuits.
A system to control power consumption of an integrated circuit, comprising:
- a clock source to generate a clock signal;
- a clock distribution network to distribute the clock signal to a plurality of local logic circuits of a processor;
- a multiple level clock gating control circuit including at least a low-level clock gating control circuit to generate, without redundant input of enabling signals for clock gating, a gated clock signal from the clock signal, and distribute the gated clock signal to one of a plurality of local logic circuits.
A method to control power consumption of a processing system, comprising:
- generating a clock signal;
- distributing the clock signal to a plurality of local logic circuits of a processor using a clock distribution network;
- and
- generating, without redundant input of enabling signals for clock gating, a gated clock signal from the clock signal, and distributing the gated clock signal to one of the plurality of local logic circuits using a multiple level clock gating control circuit including at least a high-level clock gating control circuit and a low-level clock gating control circuit.
Dependencies are inferred from the claim text.