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US 6,583,646 B1Granted
Overvoltage-tolerant interface for integrated circuits
AssigneeAltera Corporation
InventorsRakesh H. Patel, John E. Turner, Wilson Wong
Life of this patent
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Abstract
An input/output driver for interfacing directly with a voltage at a pad which is above a supply voltage for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator for preventing leakage current paths.
Claims21
A programmable logic integrated circuit comprising:
- a plurality of logic array blocks;
- a plurality of programmable interconnect lines, programmably coupled to the plurality of logic array blocks;
- and
- at least one high-voltage-tolerant interface circuit block, programmably coupled to at least one of the plurality of programmable interconnect lines, comprising:
- a first pull-up device coupled between a first supply voltage and an I/O pad;
- a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device;
- a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the pull-up device is coupled to the first control electrode of the first pull-up device;
- a first pull-down device coupled between the first control electrode of the first pull-up device and a third supply voltage;
- a second pull-down device coupled between the output pad and the third supply voltage;
- and
- a first pass device coupled between an input signal line and the second control electrode of the second pull-up device.
8 more elements
A programmable logic integrated circuit comprising:
- a plurality of logic array blocks;
- a plurality of programmable interconnect lines, programmably coupled to the plurality of logic array blocks;
- and
- at least one high-voltage-tolerant interface circuit block, programmably coupled to at least one of the plurality of programmable interconnect lines, comprising:
- a first pull-up device coupled between a first supply voltage and an I/O pad;
- a second pull-up device coupled between a second supply voltage and a first control electrode of the first pull-up device;
- a third pull-up device coupled between the second supply voltage and a second control electrode of the second pull-up device, wherein a third control electrode of the third pull-up device is coupled to the first control electrode of the first pull-up device;
- a first pull-down device coupled between the I/O pad and a first node, wherein a control electrode of the first pull-down device is coupled to the first supply voltage;
- and
- a second pull-down device coupled between the first node and a third supply voltage.
7 more elements
A high-voltage-tolerant interface circuit for an integrated circuit comprising:
- a first transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to an I/O pad and the source is coupled to a first supply voltage;
- a second transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor and the source is coupled to a second supply voltage;
- a third transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the source is coupled to the second supply, the gate is coupled to the gate of the fir transistor, and the body is coupled to the body of the second transistor and to the second supply voltage;
- and
- a four transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the I/O pad, the source is coupled to a third supply voltage, and
- the gate of the fourth transistor has an oxide thickness that is greater than an oxide thickness of another transistor of the integrated circuit.
3 more elements
A high-voltage-tolerant interface circuit for an integrated circuit comprising:
- a first transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to an I/O pad and the source is coupled to a first supply voltage;
- a second transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the first transistor and the source is coupled to a second supply voltage;
- a third transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to the gate of the second transistor, the source is coupled to the second supply, the gate is coupled to the gate of the first transistor, and the body is coupled to the body of the second transistor;
- and
- a fourth transistor having a drain, a gate, a source, and a body, wherein the drain is coupled to gate of the second transistor and the gate is coupled to the first supply voltage.
2 more elements
Dependencies are inferred from the claim text.