Back to results
US 6,583,518 B2Granted
Cross-diffusion resistant dual-polycide semiconductor structure and method
AssigneeMicron Technology, Inc.
InventorsJigish D. Trivedi, Zhongze Wang, Todd R. Abbott, Chih-Chen Cho
Life of this patent
Estimating the term…
Abstract
A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first region at an interface doped with a second dopant. A region of discontinuity is then formed in the conductive layer located away from the interface. The conductive layer formed over the polysilicon gate overlaps the interface to provide electrical continuity between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion.
Claims45
A semiconductor structure, comprising:
- a polysilicon gate having first and second regions adjoining at an interface, the first region having a first conductivity-type and the second region having a second conductivity type;
- and
- a conductive layer formed over the polysilicon gate having a first conductive region overlapping the interface to provide electrical continuity between the first and second regions of the polysilicon gate, and further having a second conductive region discontinuous from the first conductive region.
A semiconductor structure, comprising:
- a polysilicon layer having first and second adjoining regions, the first region having a first conductivity-type and the second region having a second conductivity-type opposite of the first conductivity-type;
- and
- a silicide layer formed over the polysilicon layer for electrically coupling the first and second regions thereof, the silicide layer having a discontinuous region located away from an interface of the first and second adjoining regions and exposing a portion of the polysilicon layer.
A semiconductor structure, comprising:
- a substrate of a first conductivity-type;
- a well region formed in the substrate and having a second conductivity-type opposite of the first conductivity-type;
- and
- a polycide gate formed over the substrate and well region, the polycide gate comprising:
- a first region located over the well region and having the second conductivity-type;
- a second region adjoining the first region located over the substrate, the second region having the first conductivity-type;
- and
- a silicide layer spanning an interface between the first and second regions for electrically coupling the first and second regions, the silicide layer having a region of discontinuity formed at a location other than over the interface.
5 more elements
A semiconductor structure, comprising:
- a polysilicon layer having a first region of a first conductivity-type and a second region of a second conductivity-type adjoining the first region at an interface;
- and
- a discontinuous silicide layer for electrically coupling the first and second regions of the polysilicon layer, the discontinuity formed proximate the interface between the first and second regions.
A semiconductor structure, comprising:
- a gate formed from polysilicon and having first and second regions adjoining at an interface, the first region having a first conductivity-type and a second region having a second conductivity-type;
- and
- a silicide layer formed over the gate and spanning the interface, the silicide layer having a region of discontinuity formed distant the interface.
A memory cell, comprising:
- a polycide gate formed over the substrate and well region, the polycide gate including:
- a first region of a first conductivity-type;
- a second region of a second conductivity-type adjoining the first region;
- and
- a silicide layer spanning an interface between the first and second regions for electrically coupling the first and second regions, the silicide layer having a region of discontinuity formed at a location other than over the interface.
2 more elements
A memory device, comprising:
- read and write circuitry;
- addressing circuitry;
- and
- a memory array coupled to the read and write circuitry and the addressing circuitry, the memory array having at least one memory cell comprising:
- a polysilicon gate having first and second regions adjoining at an interface, the first region having a first conductivity-type and the second region having a second conductivity type;
- and
- a silicide layer formed over the polysilicon gate having a first silicide region overlapping the interface to provide electrical continuity between the first and second regions of the polysilicon gate, and further having a second region discontinuous from the first silicide region.
4 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising:
- read and write circuitry;
- addressing circuitry;
- and
- a memory array coupled to the read and write circuitry and the addressing circuitry, the memory array having at least one memory cell comprising:
- a polysilicon gate having first and second regions adjoining at an interface, the first region having a first conductivity-type and the second region having a second conductivity type;
- and
- a silicide layer formed over the polysilicon gate having a first silicide region overlapping the interface to provide electrical continuity between the first and second regions of the polysilicon gate, and further having a second region discontinuous from the first silicide region.
9 more elements
Dependencies are inferred from the claim text.